From: Sebastien Boeuf <sebastien.bo...@intel.com> Following the model from the Xen target, CloudHv is generated as a PVH ELF binary to take advantage of the PVH specification, which requires less emulation from the VMM.
The fdf include file CloudHvElfHeader.fdf.inc has been generated from the following commands: $ gcc -D PVH64 -o elf_gen OvmfPkg/OvmfXenElfHeaderGenerator.c $ ./elf_gen 4194304 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc Signed-off-by: Sebastien Boeuf <sebastien.bo...@intel.com> --- OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc | 54 ++++++++++++++++++++++++ OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.fdf | 15 +++++-- 3 files changed, 66 insertions(+), 5 deletions(-) create mode 100644 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc diff --git a/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc b/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc new file mode 100644 index 0000000000..8377e30bdc --- /dev/null +++ b/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc @@ -0,0 +1,54 @@ +## @file +# FDF include file that defines a PVH ELF header. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +DATA = { + # ELF file header + 0x7f, 0x45, 0x4c, 0x46, 0x02, 0x01, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, + 0xd0, 0xff, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, # hdr.e_entry + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + # ELF Program segment headers + # - Load segment + 0x01, 0x00, 0x00, 0x00, + 0x07, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + # - ELFNOTE segment + 0x04, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + # XEN_ELFNOTE_PHYS32_ENTRY + 0x04, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x12, 0x00, 0x00, 0x00, + 0x58, 0x65, 0x6e, 0x00, + 0xd0, 0xff, 0x4f, 0x00 +} diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 3172100310..b4d855d80f 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -631,7 +631,7 @@ # ################################################################################ [Components] - OvmfPkg/ResetVector/ResetVector.inf + OvmfPkg/XenResetVector/XenResetVector.inf # # SEC Phase modules diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fdf index 0974e76ac8..282bcf8634 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.fdf +++ b/OvmfPkg/CloudHv/CloudHvX64.fdf @@ -14,8 +14,8 @@ !include OvmfPkg/OvmfPkgDefines.fdf.inc # -# Build the variable store and the firmware code as one unified flash device -# image. +# This will allow the flash device image to be recognize as an ELF, with first +# an ELF headers, then the firmware code. # [FD.CLOUDHV] BaseAddress = $(FW_BASE_ADDRESS) @@ -24,7 +24,14 @@ ErasePolarity = 1 BlockSize = $(BLOCK_SIZE) NumBlocks = $(FW_BLOCKS) -0x00000000|$(FVMAIN_SIZE) +# +# Leaving 4kiB for the PVH ELF header. This is more than enough. +# +0x00000000|0x00001000 + +!include CloudHvElfHeader.fdf.inc + +0x00001000|$(FVMAIN_SIZE) FV = FVMAIN_COMPACT $(SECFV_OFFSET)|$(SECFV_SIZE) @@ -114,7 +121,7 @@ READ_LOCK_STATUS = TRUE # INF OvmfPkg/Sec/SecMain.inf -INF RuleOverride=RESET_VECTOR OvmfPkg/ResetVector/ResetVector.inf +INF RuleOverride=RESET_VECTOR OvmfPkg/XenResetVector/XenResetVector.inf ################################################################################ [FV.PEIFV] -- 2.32.0 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. NANTERRE Capital: 4,572,000 Euros This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87229): https://edk2.groups.io/g/devel/message/87229 Mute This Topic: https://groups.io/mt/89500837/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-