[+cc: Tobin]
Hi Brijesh,
On 30/04/2021 14:51, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> When AMD SEV is enabled in the guest VM, a hypervisor need to insert a
> secrets page.
>
> When SEV-SNP is enabled, the secrets page contains the VM platform
> commun
Acked-by: Jiewen Yao
Need ARM expert to comment if it is OK to refer AArch64 for ARM?
Thank you
Yao Jiewen
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Etienne
> Carriere
> Sent: Tuesday, May 4, 2021 11:21 PM
> To: devel@edk2.groups.io
> Cc: Achin Gupta ; Ard Biesheuv
Reviewed-by: Jiewen Yao
> -Original Message-
> From: Agrawal, Sachin
> Sent: Wednesday, May 5, 2021 1:55 AM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen ; Wang, Jian J ;
> Lu, XiaoyuX ; Jiang, Guomin ;
> Agrawal, Sachin
> Subject: [PATCH v3 1/1] CryptoPkg: BaseCryptLib: Add RSA PSS veri
On 5/4/21 3:28 PM, Brijesh Singh wrote:
> On 5/4/21 2:55 PM, Brijesh Singh via groups.io wrote:
>> On 5/4/21 2:07 PM, Brijesh Singh via groups.io wrote:
Return EFI_UNSUPPORTED (0x8000_0003), or even EFI_NO_MAPPING
(0x8000_0017), for value 6 (FAIL_SIZEMISMATCH).
>>> I am not sure if we r
On 5/4/21 3:06 PM, Sami Mujawar wrote:
+#if defined (MDE_CPU_AARCH64)
+
+/**
+ Reads the ID_AA64ISAR0 Register.
+
+ @return The contents of the ID_AA64ISAR0 Register
+
+**/
+UINT64
+EFIAPI
+ArmReadIdIsar0 (
+ VOID
+ );
+
[SAMI] Should this function be part of ArmLib?
[/SAMI]
It's currentl
Hi Rebecca,
Please see my response inline marked [SAMI].
Regards,
Sami Mujawar
On 28/04/2021 09:44 PM, Rebecca Cran wrote:
Make BaseRngLib more generic by moving x86 specific functionality from
BaseRng.c into Rand/RdRand.c, and adding AArch64/Rndr.c, which supports
the optional ARMv8.5 RNG in
Hi Rebecca,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 28/04/2021 09:44 PM, Rebecca Cran wrote:
Add support for the optional ARMv8.5 RNDR and RNDRRS instructions that
are a part of FEAT_RNG to BaseLib, and add a function to read the ISAR0
register which indicates
On 5/4/21 2:55 PM, Brijesh Singh via groups.io wrote:
> On 5/4/21 2:07 PM, Brijesh Singh via groups.io wrote:
>>> Return EFI_UNSUPPORTED (0x8000_0003), or even EFI_NO_MAPPING
>>> (0x8000_0017), for value 6 (FAIL_SIZEMISMATCH).
>> I am not sure if we really want to do this. You will see later in t
On 5/4/21 2:07 PM, Brijesh Singh via groups.io wrote:
>> Return EFI_UNSUPPORTED (0x8000_0003), or even EFI_NO_MAPPING
>> (0x8000_0017), for value 6 (FAIL_SIZEMISMATCH).
> I am not sure if we really want to do this. You will see later in the
> patches that in some cases the PVALIDATE will return a
On 05/03/21 21:35, Rebecca Cran wrote:
> I noticed the ShellBinPkg zip file has stopped being uploaded to
> https://github.com/tianocore/edk2/releases for newer tags: the most
> recent release that has it is edk2-stable202002.
>
> Was that deliberate? I can easily build it myself, but was wonderin
On 05/04/21 13:32, Pintu Agarwal wrote:
> Hi,
> Is it possible to boot UEFI on a qemu arm based emulator?
> Since I am working from home and my uefi related work leads to device crash
> many times, which becomes painful for me.
>
> So I wanted to do all my experiments on a qemu environment before
On 5/4/21 8:58 AM, Laszlo Ersek wrote:
> On 04/30/21 13:51, Brijesh Singh wrote:
>> BZ:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275&data=04%7C01%7Cbrijesh.singh%40amd.com%7C6ceeec6c984d468bb87908d90f04b789%7C3dd8961fe4884
On 5/4/21 7:33 AM, Laszlo Ersek wrote:
> On 04/30/21 13:51, Brijesh Singh wrote:
>> BZ:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275&data=04%7C01%7Cbrijesh.singh%40amd.com%7Cbb2eaad10f574a464cb008d90ef8e5b4%7C3dd8961fe4884
On 05/04/21 16:48, Tom Lendacky wrote:
>
>
> On 5/4/21 8:59 AM, Laszlo Ersek wrote:
>> On 05/04/21 14:33, Laszlo Ersek wrote:
>>> On 04/30/21 13:51, Brijesh Singh wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3
On 05/04/21 10:31, Sami Mujawar wrote:
> Hi Laszlo,
>
> On Thu, Apr 22, 2021 at 06:56 AM, Laszlo Ersek wrote:
>
>>
>> 5) "Cloud Hypervisor" is not something that I can justifiably spend
>> much time on. I'm willing to review this series at the level at which
>> I've reviewed (for example) XenPVH
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3314
This patch uses Openssl's EVP API's to perform RSASSA-PSS verification
of a binary blob.
Cc: Jiewen Yao
Cc: Jian J Wang
Cc: Xiaoyu Lu
Cc: Guomin Jiang
Signed-off-by: Sachin Agrawal
---
Notes:
v3:
- Fixed gcc compilation erro
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3314
This patch uses Openssl's EVP API's to perform RSASSA-PSS verification
of a binary blob.
Patch v1 Cover Letter :
https://edk2.groups.io/g/devel/message/74286?p=,,,20,0,0,0::Created,,sachin,20,2,0,82225507
Patch v2 Cover Letter :
https:/
This change allows to build StandaloneMmPkg components for 32bit Arm
StandaloneMm firmware.
This change mainly moves AArch64/ source files to Arm/ side directory
for several components: StandaloneMmCpu, StandaloneMmCoreEntryPoint
and StandaloneMmMemLib. The source file is built for both 32b and 6
Use intermediate (UINTN) cast when casting int from/to pointer. This
is needed as UINT64 values cast from/to 32bit pointer for 32bit
architectures.
Cc: Achin Gupta
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Sughosh Ganu
Signed-off-by: Etienne Carriere
---
Stan
Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit
function IDs as per SMCCC specification. Defines also generic ARM
SVC identifier macros to wrap 32bit or 64bit identifiers upon target
built architecture.
Cc: Achin Gupta
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sughosh Ganu
Si
This series targets building StandaloneMM package for 32bit ARM
architectures. The main parts of the changes move AArch64/*
files to paths suitable for both 32bit and 64bit Arm machines.
Because these changes move file paths, some other edk2 related
source trees must be updated. Up to my knowledge
Change GenFv for Arm architecture to generate a specific jump
instruction as image entry instruction, when the target entry label
is assembled with Thumb instruction set. This is possible since
SecCoreEntryAddress value fetched from the PE32 as its LSBit set when
the entry instruction executes in T
Changes in ArmPkg to prepare building StandaloneMm firmware for
32bit Arm architectures.
Adds MmCommunicationDxe driver and ArmMmuPeiLib and
ArmmmuStandaloneMmLib libraries to the list of the standard
components build for ArmPkg on when ARM architectures.
Changes path of source file AArch64/ArmMm
On 5/4/21 8:59 AM, Laszlo Ersek wrote:
> On 05/04/21 14:33, Laszlo Ersek wrote:
>> On 04/30/21 13:51, Brijesh Singh wrote:
>>> BZ:
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275&data=04%7C01%7Cthomas.lendacky%40amd.com%7Cf
On 05/04/21 15:58, Laszlo Ersek wrote:
> The leading comment block of the function is supposed to explain these
> associations:
>
> @retval EFI_SUCCESSSuccessful completion (regardless of
> whether the Validated bit changed state).
> @retval INVALID_PARAME
On 05/04/21 14:33, Laszlo Ersek wrote:
> On 04/30/21 13:51, Brijesh Singh wrote:
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>>
>> The Page State Change NAE exit will be used by the SEV-SNP guest to
>> request a page state change using the GHCB protocol. See the GHCB
>> spec section
On 04/30/21 13:51, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> The PVALIDATE instruction validates or rescinds validation of a guest
> page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS
> bits OF, ZF, AF, PF and SF are set based on this re
Hi,
Is it possible to boot UEFI on a qemu arm based emulator?
Since I am working from home and my uefi related work leads to device crash
many times, which becomes painful for me.
So I wanted to do all my experiments on a qemu environment before I verify
the final changes on a real hardware.
So, I
On 04/30/21 13:51, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
>
> The Page State Change NAE exit will be used by the SEV-SNP guest to
> request a page state change using the GHCB protocol. See the GHCB
> spec section 4.1.6 and 2.3.1 for more detail on the struct
Hi Pranav,
For the serie aswell:
Reviewed-by: Pierre Gondois
Regards,
Pierre
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Hi Laszlo,
On Thu, Apr 22, 2021 at 06:56 AM, Laszlo Ersek wrote:
>
> 5) "Cloud Hypervisor" is not something that I can justifiably spend
> much time on. I'm willing to review this series at the level at which
> I've reviewed (for example) XenPVH or Bhyve in the past, mainly focusing
> on style a
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