On 5/4/21 8:59 AM, Laszlo Ersek wrote:
> On 05/04/21 14:33, Laszlo Ersek wrote:
>> On 04/30/21 13:51, Brijesh Singh wrote:
>>> BZ:
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275&data=04%7C01%7Cthomas.lendacky%40amd.com%7Cf400bca14b6f4f138a1908d90f05090f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637557336582189771%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=bjXNVWGpurRGUZkjemvDQR%2FYnEQRG9ENN22jUjtkNP0%3D&reserved=0
>>>
>>> The Page State Change NAE exit will be used by the SEV-SNP guest to
>>> request a page state change using the GHCB protocol. See the GHCB
>>> spec section 4.1.6 and 2.3.1 for more detail on the structure
>>> definitions.
>>>
>>> Cc: James Bottomley <j...@linux.ibm.com>
>>> Cc: Min Xu <min.m...@intel.com>
>>> Cc: Jiewen Yao <jiewen....@intel.com>
>>> Cc: Tom Lendacky <thomas.lenda...@amd.com>
>>> Cc: Jordan Justen <jordan.l.jus...@intel.com>
>>> Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
>>> Cc: Laszlo Ersek <ler...@redhat.com>
>>> Cc: Erdem Aktas <erdemak...@google.com>
>>> Signed-off-by: Brijesh Singh <brijesh.si...@amd.com>
>>> ---
>>> MdePkg/Include/Register/Amd/Fam17Msr.h | 15 ++++++++++
>>> MdePkg/Include/Register/Amd/Ghcb.h | 29 ++++++++++++++++++++
>>> 2 files changed, 44 insertions(+)
>>>
>>> diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h
>>> b/MdePkg/Include/Register/Amd/Fam17Msr.h
>>> index e19bd04b6c..432cee2feb 100644
>>> --- a/MdePkg/Include/Register/Amd/Fam17Msr.h
>>> +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
>>> @@ -58,6 +58,19 @@ typedef union {
>>> UINT64 GuestFrameNumber:52;
>>> } GhcbGpaRegister;
>>>
>>> + struct {
>>> + UINT64 Function:12;
>>> + UINT64 GuestFrameNumber:40;
>>> + UINT64 Operation:4;
>>> + UINT64 Reserved:8;
>>> + } SnpPageStateChangeRequest;
>>> +
>>> + struct {
>>> + UINT32 Function:12;
>>> + UINT32 Reserved:20;
>>> + UINT32 ErrorCode;
>>> + } SnpPageStateChangeResponse;
>>> +
>>> VOID *Ghcb;
>>>
>> This matches section 2.3.1 in rev 2.00.
>>
>>> UINT64 GhcbPhysicalAddress;
>>> @@ -69,6 +82,8 @@ typedef union {
>>> #define GHCB_INFO_CPUID_RESPONSE 5
>>> #define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18
>>> #define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE 19
>>> +#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST 20
>>> +#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE 21
>>> #define GHCB_HYPERVISOR_FEATURES_REQUEST 128
>>> #define GHCB_HYPERVISOR_FEATURES_RESPONSE 129
>>> #define GHCB_INFO_TERMINATE_REQUEST 256
>>
>> Matches section 2.3.1.
>>
>>> diff --git a/MdePkg/Include/Register/Amd/Ghcb.h
>>> b/MdePkg/Include/Register/Amd/Ghcb.h
>>> index 2d64a4c28f..1e7c0daed3 100644
>>> --- a/MdePkg/Include/Register/Amd/Ghcb.h
>>> +++ b/MdePkg/Include/Register/Amd/Ghcb.h
>>> @@ -54,6 +54,7 @@
>>> #define SVM_EXIT_NMI_COMPLETE 0x80000003ULL
>>> #define SVM_EXIT_AP_RESET_HOLD 0x80000004ULL
>>> #define SVM_EXIT_AP_JUMP_TABLE 0x80000005ULL
>>> +#define SVM_EXIT_SNP_PAGE_STATE_CHANGE 0x80000010ULL
>>> #define SVM_EXIT_HYPERVISOR_FEATURES 0x8000FFFDULL
>>> #define SVM_EXIT_UNSUPPORTED 0x8000FFFFULL
>>>
>>
>> Matches "Table 5. List of Supported Non-Automatic Events".
>>
>>> @@ -160,4 +161,32 @@ typedef union {
>>> #define GHCB_HV_FEATURES_SNP_AP_CREATE
>>> (GHCB_HV_FEATURES_SNP | BIT1)
>>> #define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION
>>> (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)
>>> #define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER
>>> (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)
>>> +
>>> +// SNP Page State Change
>>
>> (1) Comment style.
>>
>>> +#define SNP_PAGE_STATE_MAX_NPAGES 4095
>>> +#define SNP_PAGE_STATE_MAX_ENTRY 253
>>> +#define SNP_PAGE_STATE_PRIVATE 1
>>> +#define SNP_PAGE_STATE_SHARED 2
>>> +#define SNP_PAGE_STATE_PSMASH 3
>>> +#define SNP_PAGE_STATE_UNSMASH 4
>>
>> (2) The PSMASH and UNSMASH operations are not documented in the rev 2.00
>> spec, in the GHCB MSR protocol. That's probably because PSMASH and
>> UNSMASH can only be defined in terms of 2MB pages, and
>> GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST is suitable only for individual,
>> 4KB pages. I think it would be useful to point out somehow here that
>> PSMASH and UNSMASH are restricted to the GHCB shared area protocol
>> (perhaps extend the leading comment on this block of macros).
>>
>> (3) I don't understand what "MAX_NPAGES" stands for (4095). The rest of
>> the series never uses the macro, and I can't associate it with anything
>> from the spec. If the macro is supposed to relate to the 4KB / 2MB page
>> smashing / splitting, then its replacement text should be 512. Unless
>> the macro corresponds to a definition in the spec, I think we should
>> drop it.
>>
>>> +
>>> +typedef PACKED struct {
>>> + UINT64 CurrentPage:12;
>>> + UINT64 GuestFrameNumber:40;
>>> + UINT64 Op:4;
>>> + UINT64 PageSize:1;
>>> + UINT64 Rsvd: 7;
>>> +} SNP_PAGE_STATE_ENTRY;
>>> +
>>> +typedef PACKED struct {
>>> + UINT16 CurrentEntry;
>>> + UINT16 EndEntry;
>>> + UINT32 Rsvd;
>>> +} SNP_PAGE_STATE_HEADER;
>>
>> (4) We tend to write
>>
>> #pragma pack (1)
>> ...
>> #pragma pack ()
>>
>> rather than PACKED -- but anyway, is packing really necessary? "Natural
>> alignment" is required in edk2. I'm OK with packing, but I think the
>> pragma is the preferred form.
>>
>> (5) Please spell out both "Rsvd" fields above as "Reserved".
>>
>> (6) Stray space character in "Rsvd: 7".
>>
>> (7) The field name "Op" is inconsistent with the other field name
>> "Operation".
>>
>> (8) I think there is a bug (typo) in the rev 2.00 spec, in 4.1.6 "SNP
>> Page State Change": it says
>>
>> ... calculated from the supplied guest physical frame number (GFN) for
>> the requested page size (GPA = GFN << 12).
>>
>> But, if you can choose 2MB page size in the request, then the (GPA = GFN
>> << 12) formula is not g
>
> Sorry, unfinished sentence: I meant that the formula was not generally
> correct.
Actually, for any page size, the GPA for any GFN is GFN << 12.
For the SNP Page State Change NAE event, it is up to the hypervisor to
ensure that the GFN/GPA supplied is aligned appropriately for the
requested page size (see 4.1.6 of the GHCB spec where the page operations
are defined). A GFN is naturally 4K aligned, so only a 2MB page size needs
GFN/GPA alignment validation.
For the SNP Page State Change MSR protocol, only a 4K page size is supported.
Thanks,
Tom
>
> Thanks
> Laszlo
>
>>
>> (9) If my understanding of the spec is correct, "EndEntry" has
>> *inclusive* meaning. That's unusual. Any particular reason for not
>> making "EndEntry" exclusive (in the spec)?
>>
>>> +
>>> +typedef struct {
>>> + SNP_PAGE_STATE_HEADER Header;
>>> + SNP_PAGE_STATE_ENTRY Entry[SNP_PAGE_STATE_MAX_ENTRY];
>>> +} SNP_PAGE_STATE_CHANGE_INFO;
>>> +
>>> #endif
>>>
>>
>> Yes, this looks OK. Size is 2+2+4+253*8 = 2032 bytes, which matches the
>> size of GHCB.SharedBuffer.
>>
>> (10) However, *if* you decide to declare SNP_PAGE_STATE_ENTRY and
>> SNP_PAGE_STATE_HEADER explicitly as packed, then you should do the same
>> for SNP_PAGE_STATE_CHANGE_INFO.
>>
>> (11) Like I mentioned earlier, it's probably helpful if you start the
>> subject line with
>>
>> MdePkg/Register/Amd: ...
>>
>> on all of these MdePkg patches. If that becomes too tight, for some of
>> the MdePkg patches, then I suggest "MdePkg/Amd: ..." (i.e., drop
>> "Register").
>>
>> Thanks
>> Laszlo
>>
>
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