Hello Ard Biesheuvel,
Would you please review this change?
Thank you,
Irene
-Original Message-
From: Irene Park
Sent: Friday, June 5, 2020 11:23 PM
To: devel@edk2.groups.io
Cc: Irene Park
Subject: [PATCH] ArmPlatformPkg/PL011UartLib: Add PCD for FIFO depth
From: Irene Park
PL011UartL
From: Irene Park
PL011UartLib determines its FIFO depth based on the PID2 value but
the register PID2 is not mandatory in the SBSA spec.
This change adds a new 32bit PCD reference to define a FIFO depth and
make PL011UartLib available for the custom UART which is compliant
to the SBSA spec but do
When an image fails Secure Boot validation, LoadImage() returns
EFI_SECURITY_VIOLATION if the platform policy is
DEFER_EXECUTE_ON_SECURITY_VIOLATION.
If the platform policy is DENY_EXECUTE_ON_SECURITY_VIOLATION, then
LoadImage() returns EFI_ACCESS_DENIED (and the image does not remain
loaded).
(B
On 6/5/20 11:18 PM, Kinney, Michael D wrote:
Ard,
Thanks for the notification. We will investigate.
Thanks Mike
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Ard,
Thanks for the notification. We will investigate.
Mike
> -Original Message-
> From: devel@edk2.groups.io On
> Behalf Of Ard Biesheuvel
> Sent: Friday, June 5, 2020 2:01 PM
> To: Kinney, Michael D ;
> devel@edk2.groups.io; ler...@redhat.com; Leif Lindholm
> ; Gao, Liming
> Subject
Hello all,
I am seeing weird behavior trying to push some changes:
https://github.com/tianocore/edk2/pull/664
https://github.com/tianocore/edk2/pull/665
Many checks are failing with weird errors like below.
Was anyone aware that this is broken, and is it being fixed?
Thanks,
Ard.
@azure-pip
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will th
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
A hypervisor is not allowed to update an SEV-ES guests register state,
so when booting an SEV-ES guest AP, the hypervisor is not allowed to
set the RIP to the guest requested value. Instead, an SEV-ES AP must be
transition from 64-bit long mo
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Before UEFI transfers control to the OS, it must park the AP. This is
done using the AsmRelocateApLoop function to transition into 32-bit
non-paging mode. For an SEV-ES guest, a few additional things must be
done:
- AsmRelocateApLoop must b
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
A hypervisor is not allowed to update an SEV-ES guest's register state,
so when booting an SEV-ES guest AP, the hypervisor is not allowed to
set the RIP to the guest requested value. Instead an SEV-ES AP must be
re-directed from within the gu
Register reviewers for the SEV-related files in OvmfPkg.
Cc: Andrew Fish
Cc: Laszlo Ersek
Cc: Leif Lindholm
Cc: Michael D Kinney
Cc: Brijesh Singh
Reviewed-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
Maintainers.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Maint
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
After having transitioned from UEFI to the OS, the OS will need to boot
the APs. For an SEV-ES guest, the APs will have been parked by UEFI using
GHCB pages allocated by UEFI. The hypervisor will write to the GHCB
SW_EXITINFO2 field of the GH
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
When starting APs in an SMP configuration, the AP needs to know if it is
running as an SEV-ES guest in order to assign a GHCB page.
Add a field to the CPU_MP_DATA structure that will indicate if SEV-ES is
enabled. This new field is set durin
> On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal
> >
> > for LS1043A SOC the DCFG registers are read in big endian format.
> > However current Platofmr PLL calculation is being done assuing the
>
> Platform? assu
Hi,
I'd like to ask for comments before I develop the actual code - currently
we have 2 workarounds done specifically for Linux:
a. ECAM shift in PCIE
b. SPCR address space definition
Both above are not needed e.g. in FreeBSD and I was requested to add their
optional disabling. The idea is to add
pt., 5 cze 2020 o 16:46 Ard Biesheuvel napisał(a):
>
> On 6/5/20 3:27 PM, Marcin Wojtas wrote:
> > pt., 5 cze 2020 o 15:08 Ard Biesheuvel napisał(a):
> >>
> >> On 6/5/20 1:54 PM, Marcin Wojtas wrote:
> >>> Hi Ard,
> >>>
> >>>
> >>> czw., 4 cze 2020 o 23:35 Ard Biesheuvel
> >>> napisał(a):
> >>>
On 6/5/20 3:27 PM, Marcin Wojtas wrote:
pt., 5 cze 2020 o 15:08 Ard Biesheuvel napisał(a):
On 6/5/20 1:54 PM, Marcin Wojtas wrote:
Hi Ard,
czw., 4 cze 2020 o 23:35 Ard Biesheuvel napisał(a):
To ensure that platforms incorporating MvI2cDxe will keep working
as intended once the platform B
On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal
>
> for LS1043A SOC the DCFG registers are read in big endian format.
> However current Platofmr PLL calculation is being done assuing the
Platform? assuming
> littl
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a NPF intercept for an NPT entry with a reserved bit set
generates a #VC exception. This condition is assumed to be an MMIO access.
VMGEXIT must be used to allow the hypervisor to handle this intercept.
Add support to construct
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Protect the memory used by an SEV-ES guest when S3 is supported. This
includes the page table used to break down the 2MB page that contains
the GHCB so that it can be marked un-encrypted, as well as the GHCB
area.
Regarding the lifecycle of
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Allocate memory for the GHCB pages and the per-CPU variable pages during
SEV initialization for use during Pei and Dxe phases. The GHCB page(s)
must be shared pages, so clear the encryption mask from the current page
table entries. Upon succe
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a WBINVD intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Acked-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
The SEV support will clear the C-bit from non-RAM areas. The early GDT
lives in a non-RAM area, so when an exception occurs (like a #VC) the GDT
will be read as un-encrypted even though it is encrypted. This will result
in a failure to be ab
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a DR7 read or write intercept generates a #VC exception.
The #VC handler must provide special support to the guest for this. On
a DR7 write, the #VC handler must cache the value and issue a VMGEXIT
to notify the hypervisor of th
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
During BSP startup, the reset vector code will issue a CPUID instruction
while in 32-bit mode. When running as an SEV-ES guest, this will trigger
a #VC exception.
Add exception handling support to the early reset vector code to catch
these e
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a INVD intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Acked-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
--
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
An SEV-ES guest will generate a #VC exception when it encounters a
non-automatic exit (NAE) event. It is expected that the #VC exception
handler will communicate with the hypervisor using the GHCB to handle
the NAE event.
NAE events can occu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
A GHCB page is needed during the Sec phase, so this new page must be
created. Since the #VC exception handler routines assume that a per-CPU
variable area is immediately after the GHCB, this per-CPU variable area
must also be created. Since t
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Create a function that can be used to determine if the VM is running
as an SEV-ES guest.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Reviewed-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
OvmfPkg/Include/Library/MemEncrypt
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
The flash detection routine will attempt to determine how the flash
device behaves (e.g. ROM, RAM, Flash). But when SEV-ES is enabled and
the flash device behaves as a ROM device (meaning it is marked read-only
by the hypervisor), this check
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a VMMCALL intercept generates a #VC exception. VMGEXIT must
be used to allow the hypervisor to handle this intercept.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Acked-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Reserve a fixed area of memory for SEV-ES use and set a fixed PCD,
PcdSevEsWorkAreaBase, to this value.
This area will be used by SEV-ES support for two purposes:
1. Communicating the SEV-ES status during BSP boot to SEC:
Using a byte
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a MWAIT/MWAITX intercept generates a #VC exception.
VMGEXIT must be used to allow the hypervisor to handle this intercept.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Acked-by: Laszlo Ersek
Signed-off-by: Tom Lend
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Protect the SEV-ES work area memory used by an SEV-ES guest.
Regarding the lifecycle of the SEV-ES memory area:
PcdSevEsWorkArea
(a) when and how it is initialized after first boot of the VM
If SEV-ES is enabled, the SEV-ES area is ini
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
When SEV-ES is enabled, then SEV is also enabled. Add support to the SEV
initialization function to also check for SEV-ES being enabled, and if
enabled, set the SEV-ES enabled PCD (PcdSevEsIsEnabled).
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a MONITOR/MONITORX intercept generates a #VC exception.
VMGEXIT must be used to allow the hypervisor to handle this intercept.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Acked-by: Laszlo Ersek
Signed-off-by: Tom
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a RDPMC intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Acked-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
-
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a RDTSCP intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Acked-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Currently, the OVMF code relies on the hypervisor to enable the cache
support on the processor in order to improve the boot speed. However,
with SEV-ES, the hypervisor is not allowed to change the CR0 register
to enable caching.
Update the O
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a RDTSC intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Cc: Jordan Justen
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Acked-by: Laszlo Ersek
Signed-off-by: Tom Lendacky
-
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Create an SEV-ES workarea PCD. This PCD will be used for BSP communication
during SEC and for AP startup during PEI and DXE phases, the latter is the
reason for creating it in the UefiCpuPkg.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Sign
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Add support to the #VC exception handler to handle string IO. This
requires expanding the IO instruction parsing to recognize string based
IO instructions as well as preparing an un-encrypted buffer to be used
to transfer (either to or from t
The base VmgExitLib library provides a default limited interface. As it
does not provide full support, create an OVMF version of this library to
begin the process of providing full support of SEV-ES within OVMF.
SEV-ES support is only provided for X64 builds, so only OvmfPkgX64.dsc is
updated to m
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.
Add support to construct the required GHCB values to support a CPUID NAE
event. Additionally, CPUID 0x_000d
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
GHCB pages must be mapped as shared pages, so modify the process of
creating identity mapped pagetable entries so that GHCB entries are
created without the encryption bit set. The GHCB range consists of
two pages per CPU, the first being the
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a MSR_PROT intercept generates a #VC exception. VMGEXIT must
be used to allow the hypervisor to handle this intercept.
Add support to construct the required GHCB values to support an MSR_PROT
NAE event. Parse the instruction th
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
For SEV-ES, the GHCB page address is stored in the GHCB MSR register
(0xc0010130). Define the register and the format used for register
during GHCB protocol negotiation.
Cc: Michael D Kinney
Cc: Liming Gao
Signed-off-by: Tom Lendacky
---
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
The GHCB is used by an SEV-ES guest for communicating between the guest
and the hypervisor. Create the GHCB definition as defined by the GHCB
protocol definition.
Cc: Michael D Kinney
Cc: Liming Gao
Signed-off-by: Tom Lendacky
---
MdePkg
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
To support handling #VC exceptions and issuing VMGEXIT instructions,
create a library with functions that can be used to perform these
#VC/VMGEXIT related operations. This includes functions for:
- Handling #VC exceptions
- Preparing for
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Various CpuExceptionHandlerLib libraries will updated to use the new
VmgExitLib library. To prevent any build breakage, update the
UefiPayloadPkg DSC files that use a form of the CpuExceptionHandlerLib
library to include the VmgExitLib librar
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
VMGEXIT is a new instruction used for Hypervisor/Guest communication when
running as an SEV-ES guest. A VMGEXIT will cause an automatic exit (AE)
to occur, resulting in a #VMEXIT with an exit code value of 0x403.
Provide the necessary suppor
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a CPUID instruction requires the current value of the XCR0
register. In order to retrieve that value, the XGETBV instruction needs
to be executed.
Provide the necessary support to execute the XGETBV instruction.
Cc: Michael D
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Two new dynamic MdeModulePkg PCDs are needed to support SEV-ES under OVMF:
- PcdGhcbBase: UINT64 value that is the base address of the GHCB
allocation.
- PcdGhcbSize: UINT64 value that is the size, in by
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Various CpuExceptionHandlerLib libraries will updated to use the new
VmgExitLib library. To prevent any build breakage, update the OvmfPkg
DSC files that use a form of the CpuExceptionHandlerLib library to
include the VmgExitLib library.
Cc:
This patch series provides support for running EDK2/OVMF under SEV-ES.
Secure Encrypted Virtualization - Encrypted State (SEV-ES) expands on the
SEV support to protect the guest register state from the hypervisor. See
"AMD64 Architecture Programmer's Manual Volume 2: System Programming",
section "
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
A new dynamic UefiCpuPkg PCD is needed to support SEV-ES under OVMF:
- PcdSevEsIsEnabled: BOOLEAN value used to indicate if SEV-ES is enabled
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Signed-off-by: Tom Lendacky
---
UefiCpuPkg/UefiCpu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Add base support to handle #VC exceptions. Update the common exception
handlers to invoke the VmgExitHandleVc () function of the VmgExitLib
library when a #VC is encountered. A non-zero return code will propagate
to the targeted exception han
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a IOIO_PROT intercept generates a #VC exception. VMGEXIT
must be used to allow the hypervisor to handle this intercept.
Add support to construct the required GHCB values to support a IOIO_PROT
NAE event. Parse the instruction
pt., 5 cze 2020 o 15:08 Ard Biesheuvel napisał(a):
>
> On 6/5/20 1:54 PM, Marcin Wojtas wrote:
> > Hi Ard,
> >
> >
> > czw., 4 cze 2020 o 23:35 Ard Biesheuvel napisał(a):
> >>
> >> To ensure that platforms incorporating MvI2cDxe will keep working
> >> as intended once the platform BDS code stops
On Fri, Jun 05, 2020 at 15:01:36 +0200, Ard Biesheuvel wrote:
> On 6/5/20 6:02 PM, Meenakshi Aggarwal wrote:
> > Enable support of SATA drives on lx2160 RDB board.
> >
> > Signed-off-by: Meenakshi Aggarwal
> > ---
> > Silicon/NXP/LX2160A/LX2160A.dsc.inc | 5 +
> > Platform/NXP/L
On 6/5/20 1:54 PM, Marcin Wojtas wrote:
Hi Ard,
czw., 4 cze 2020 o 23:35 Ard Biesheuvel napisał(a):
To ensure that platforms incorporating MvI2cDxe will keep working
as intended once the platform BDS code stops calling ConnectAll(),
connect the I2C masters explicitly at EndOfDxe.
Signed-off
On 6/5/20 6:02 PM, Meenakshi Aggarwal wrote:
Enable support of SATA drives on lx2160 RDB board.
Signed-off-by: Meenakshi Aggarwal
---
Silicon/NXP/LX2160A/LX2160A.dsc.inc | 5 +
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 2 ++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
On 6/5/20 6:02 PM, Meenakshi Aggarwal wrote:
Add support of SATA controller driver which performs
controller initialization and register itself as NonDiscoverableMmioDevice
Signed-off-by: Meenakshi Aggarwal
---
Silicon/NXP/NxpQoriqLs.dec | 6 +
Silicon/NXP/NxpQoriqLs.d
On Tue, Jun 02, 2020 at 00:57:38 +0530, Wasim Khan wrote:
> From: Wasim Khan
>
> Based on the serdes protocol value in reset configuration
> word (RCW), different PCIe controllers are enabled.
> Get serdes protocol map and initialize only enabled PCIe
> controllers.
>
> Signed-off-by: Wasim Khan
On Tue, Jun 02, 2020 at 00:57:37 +0530, Wasim Khan wrote:
> From: Wasim Khan
>
> Based on serdes protocol value in reset configuration word (RCW)
> different IP blocks gets enabled in HW.
> Add SoC specific serdes configuration for LS1043A, which can be
> used by different IPs to know the enabled
On Tue, Jun 02, 2020 at 00:57:36 +0530, Wasim Khan wrote:
> From: Wasim Khan
>
> Implement SerDesHelperLib to provide helper functions which
> can be used for SoC specific serdes configuration.
>
> Signed-off-by: Wasim Khan
> ---
> Silicon/NXP/NxpQoriqLs.dec | 1
Hi Ard,
czw., 4 cze 2020 o 23:35 Ard Biesheuvel napisał(a):
>
> To ensure that platforms incorporating MvI2cDxe will keep working
> as intended once the platform BDS code stops calling ConnectAll(),
> connect the I2C masters explicitly at EndOfDxe.
>
> Signed-off-by: Ard Biesheuvel
> ---
> Buil
Thanks Liming for the integration. Change is now visible in the edk2platforms
repo:
(https://github.com/tianocore/edk2-platforms/commit/4a937016142ea084a2aad19e9bd8f1b50fab38d4)
-Original Message-
From: Gao, Liming
Sent: Wednesday, June 3, 2020 7:41 PM
To: Hernandez Beltran, Jorge ;
Add support of SATA controller driver which performs
controller initialization and register itself as NonDiscoverableMmioDevice
Signed-off-by: Meenakshi Aggarwal
---
Silicon/NXP/NxpQoriqLs.dec | 6 +
Silicon/NXP/NxpQoriqLs.dsc.inc | 10 ++
Silicon/NXP/Dri
This patchset implement SATA driver for NXP Platforms enable
SATA for LX2160A Platform.
Meenakshi Aggarwal (2):
Silicon/NXP: Add SATA controller initialization driver
Platform/NXP:LX2160: Enable support of SATA controller
Silicon/NXP/NxpQoriqLs.dec | 6 +
Silicon/NXP/L
The timezone of following cities should be updated:
Istanbul: UTC+3
Novosibirsk: UTC+7
Georgetown (Guyana): UTC-4
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dorapika Wu
---
.../UefiShellLevel2CommandsLib.uni | 12 ++--
1 file changed,
Enable support of SATA drives on lx2160 RDB board.
Signed-off-by: Meenakshi Aggarwal
---
Silicon/NXP/LX2160A/LX2160A.dsc.inc | 5 +
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 2 ++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 18 +++---
3 files changed, 22 inser
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2687
FIT specification revision 1.2 was released to the open community.
Revision 1.2 updates CSE Secure Boot Rules (section 4.12) and adds
2 new entry sub-types used to distinguish the CSE entries.
Signed-off-by: Jorge Hernandez Beltran
Re
Done. I fixed the commit message issues regarding the format and I sent the
updated patch with "git send-email --compose --to=devel@edk2.groups.io..."
command again.
I added "-v2 --annotate" to indicate it was version 2 of the patch but I guess
it didn't work, subject from new email doesn't have
Thank for the info. I tried and indeed the subject now reflects the patch
version. I already added this to my notes for future code reviews
-Original Message-
From: Gao, Liming
Sent: Wednesday, June 3, 2020 7:39 PM
To: Hernandez Beltran, Jorge ; Lohr, Paul A
; devel@edk2.groups.io
Subj
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2691
For files to be added to the tree, this feature will check
whether it has BSD plus patent license. If not, licenses listed in
Readme are also accepted but warning will be reported.
Otherwise, it should be error.
Cc: Bob Feng
Cc: Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2691
For files to be added to the tree, this feature will check
whether it has BSD plus patent license. If not, licenses listed in
Readme are also accepted but warning will be reported.
Otherwise, it should be error.
Cc: Bob Feng
Cc: Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2777
Code wrapped by DISABLE_NEW_DEPRECATED_INTERFACES is deprecated.
So remove it.
Cc: Michael D Kinney
Cc: Liming Gao
Signed-off-by: Shenglei Zhang
---
MdePkg/Library/BaseLib/String.c| 626 -
MdePkg/Library/B
Reviewed-by: Zhiguang Liu
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Michael
> Kubacki
> Sent: Wednesday, April 22, 2020 2:35 AM
> To: devel@edk2.groups.io
> Cc: Bret Barkelew ; Gao, Liming
> ; Kinney, Michael D
> Subject: [edk2-devel] [PATCH v1 1/2] MdePkg/UnitTestL
Reviewed-by: G Edhaya Chandran< edhaya.chandran@ arm.com >
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On 6/4/20 2:27 PM, Pete Batard wrote:
On 2020.06.04 10:50, Ard Biesheuvel wrote:
The BDS will connect device paths that are considered as boot options,
so there is really no reason to always connect absolutely everything.
So now that all the drivers have been updated to play nice in this
case, r
On 6/4/20 3:12 PM, Vijayenthiran Subramaniam wrote:
Supervisor Call instruction (SVC) is used by the Arm Standalone MM
environment to request services from the privileged software (such as
ARM Trusted Firmware running in EL3) and also return back to the
non-secure caller via EL3. Some Arm CPUs sp
Hello Edhaya,
Would you please kindly review this change?
Thank you,
Irene
-Original Message-
From: G Edhaya Chandran
Sent: Wednesday, June 3, 2020 3:54 AM
To: Irene Park ; devel@edk2.groups.io; Samer El-Haj-Mahmoud
Cc: eric@intel.com
Subject: RE: [edk2-devel] [PATCH] uefi-sct/SctP
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