Thanks everyone for the discussion, and thanks @thierry for bringing up the
topic of language/framework choice for the VTA core. I wish to share some of my
thoughts on this topic.
As a FPGA engineer, I mostly wrote VHDL/verilog codes for my past projects. I
must admit that I am not very famil
[quote="thierry, post:14, topic:6676, full:true"]
Finally some lower level comments for @zhanghaohit and @remotego:
* I agree with @liangfu that leveraging Chisel would be ideal in the spirit of
minimizing the number of design sources. There is an initial scaffold of the
Chisel design to work
