im Hardisty
>Sent: Wednesday, May 17, 2023 7:31 PM
>To: dev@nuttx.apache.org
>Subject: Re: Odd DMA issue
>
>Good suggestion – thanks!
>
>From: Petro Karashchenko Reply to:
>"dev@nuttx.apache.org"
>Date: Wednesday, 17 May 2023 at 19:28
>To: "dev@nuttx
Hardisty schrieb am Mi., 17. Mai 2023, 20:31:
> Good suggestion – thanks!
>
> From: Petro Karashchenko
> Reply to: "dev@nuttx.apache.org"
> Date: Wednesday, 17 May 2023 at 19:28
> To: "dev@nuttx.apache.org"
> Subject: Re: Odd DMA issue
>
> I th
Good suggestion – thanks!
From: Petro Karashchenko
Reply to: "dev@nuttx.apache.org"
Date: Wednesday, 17 May 2023 at 19:28
To: "dev@nuttx.apache.org"
Subject: Re: Odd DMA issue
I think you can try to compare versus SAMv7 SPI+DMA driver that is working
well and see
In what way?
I am concerned by a comment in the sama5 xdmac code which says:
“Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the
same transfer, however.”
They are sort of intermixed as part of the SPI exchange function – which is
near enough identical to most arm proc
I think you can try to compare versus SAMv7 SPI+DMA driver that is working
well and see if there are obvious differences.
BR,
Petro
On Wed, May 17, 2023, 9:18 PM Simon Filgis
wrote:
> D-Cache flush?
>
> --
> Ingenieurbüro-Filgis
> USt-IdNr.: DE305343278
> --
> sent by mobile phone
>
> Tim Hardi
D-Cache flush?
--
Ingenieurbüro-Filgis
USt-IdNr.: DE305343278
--
sent by mobile phone
Tim Hardisty schrieb am Mi., 17. Mai 2023, 20:05:
> I am working on getting DMA working on the SPI peripheral of the SAMA5D2.
>
> DMA reads now work well, but the writes take absolutely forever…unless I
> have
I am working on getting DMA working on the SPI peripheral of the SAMA5D2.
DMA reads now work well, but the writes take absolutely forever…unless I have
dma debug info enabled, when write transactions (to a GD25Q flash) do then work.
I’m working through it, as it sounds like a race condition or o
