I have compared the SAMv7 SPI XDMAC to SAMA5, and checked the PR and dcache suggestions from Simon Filgis and only found one discrepancy::
SAMA5 had DMACH_FLAG_MEMBURST_4 compared to SAMv7 which had DMACH_FLAG_MEMBURST_1. I won't profess to understand the detailed significance, but DMA does now work having changed it, but I see the fairly recently added DMA support for SAMA5 flexcom has DMACH_FLAG_MEMBURST_4 as well, so I will try and understand this better for sure. I am now added spi_setdelay functionality to the SAMA5 SPI driver since it was missing, and the default delays are horrendous, and I will do a PR for all of this soon. I will also do a separate PR for the GD25 driver to allow the various delays to be set via Kconfig and passed to the lower level drivers using SET_DELAY, otherwise the delays will never be set in the driver. I currently have read DMA at around 600KB/s (using dd to read from GD25 to /dev/null) and write at 79KB/s (dd from FAT formatted ramdrv to GD25 memory clocked at 103MHz). I think it should go faster, and I will probably keep plugging away at it, but 20x faster than it was last week. >-----Original Message----- >From: Tim Hardisty <t...@hardisty.co.uk> >Sent: Wednesday, May 17, 2023 7:31 PM >To: dev@nuttx.apache.org >Subject: Re: Odd DMA issue > >Good suggestion – thanks! > >From: Petro Karashchenko <petro.karashche...@gmail.com> Reply to: >"dev@nuttx.apache.org" <dev@nuttx.apache.org> >Date: Wednesday, 17 May 2023 at 19:28 >To: "dev@nuttx.apache.org" <dev@nuttx.apache.org> >Subject: Re: Odd DMA issue > >I think you can try to compare versus SAMv7 SPI+DMA driver that is >working well and see if there are obvious differences. > >BR, >Petro > >On Wed, May 17, 2023, 9:18 PM Simon Filgis <simon@ingenieurbuero- >filgis.de<mailto:si...@ingenieurbuero-filgis.de>> >wrote: > >D-Cache flush? > >-- >Ingenieurbüro-Filgis >USt-IdNr.: DE305343278 >-- >sent by mobile phone > >Tim Hardisty <t...@hardisty.co.uk<mailto:t...@hardisty.co.uk>> schrieb am >Mi., 17. Mai 2023, 20:05: > >> I am working on getting DMA working on the SPI peripheral of the >SAMA5D2. >> >> DMA reads now work well, but the writes take absolutely forever…unless >> I have dma debug info enabled, when write transactions (to a GD25Q >> flash) >do >> then work. >> >> I’m working through it, as it sounds like a race condition or other >> timing/sequence problem but if anyone by any chance has encountered >> anything similar, clues or suggestions would be most welcome! >> >> Thx, >> >> Tim >> >
