Hi Jie,
On 2024/2/26 11:07, Jie Hai wrote:
> This patch adds "filter" and "names" fields to "rte_dev_reg_info"
> structure. Names of registers in data fields can be reported and
> the registers can be filtered by their names.
>
> The new API rte_eth_dev_get_reg_info_ext() is added to support
> re
Uninitialized mbufs are enqueued to eventdev which causes segfault
on freeing the mbuf in tx adapter.
Fixed by initializing mbufs before enqueuing to eventdev.
Fixes: 46cf97e4bbfa ("eventdev: add test for eth Tx adapter")
Signed-off-by: Ganapati Kundapura
diff --git a/app/test/test_event_eth_tx
On Fri, Feb 23, 2024 at 7:30 PM Morten Brørup
wrote:
>
> Bugfix: The vlan in the bulletin does not contain a VLAN header, only the
> VLAN ID, so only copy 2 byte, not 4. The target structure has padding
> after the field, so copying 2 byte too many is effectively harmless.
> There is no need to b
Adds a devarg option to enable/disable ISM memory accesses
for reading packet count details. This option is disabled
by default, as ISM memory accesses effect throughput of
bigger size packets.
Signed-off-by: Vamsi Attunuru
---
V2 changes:
- Updated release notes and documentation
- Added missing
On Fri, Feb 23, 2024 at 8:19 PM Luca Vizzarro wrote:
>
> On 29/01/2024 13:10, Juraj Linkeš wrote:
> > Here's I'd add logged additionally as an error, as this sounds as if
> > we're changing debug to error
>
> That is also a way of doing this, but an error is an error. If we wanted
> to log the sam
Hi Jie,
On 2024/2/26 11:07, Jie Hai wrote:
> This patch adds a telemetry command for registers dump,
> and supports get registers with specified names.
> The length of the string exported by telemetry is limited
> by MAX_OUTPUT_LEN. Therefore, the filter should be more
> precise.
>
> An example u
On Fri, Feb 23, 2024 at 8:12 PM Luca Vizzarro wrote:
>
> On 29/01/2024 13:04, Juraj Linkeš wrote:
> > I'm curious, what exactly is confusing about the message?
>
> Unfortunately a bit too much time has passed... but if I remember
> correctly I think that given the great amount of arguments, whenev
https://bugs.dpdk.org/show_bug.cgi?id=1384
Bug ID: 1384
Summary: PCAP PMD reconfiguration failure
Product: DPDK
Version: 22.11
Hardware: All
OS: All
Status: UNCONFIRMED
Severity: normal
Priority:
Adds support to configure writing result to offset of the DMA
response event.
Signed-off-by: Amit Prakash Shukla
---
v3:
- Rebased and fixed compilation error.
v2:
- Added dual workslot enqueue support.
- Fixed compilation error.
drivers/common/cnxk/roc_dpi.c | 6 +-
drivers/common/
Added cnxk driver support for dma event enqueue and dequeue.
Also added changes for work queue entry completion status and
dual workslot DMA event enqueue.
Signed-off-by: Pavan Nikhilesh
Signed-off-by: Amit Prakash Shukla
---
v3:
- Rebased and fixed compilation error.
v2:
- Added dual workslot
Added support of dma driver callback assignment to eventdev
enqueue and dequeue. The change also defines dma adapter
capabilities function.
Depends-on: series-30612 ("lib/dmadev: get DMA device using device ID")
Signed-off-by: Amit Prakash Shukla
---
v3:
- Rebased and fixed compilation error.
v
https://bugs.dpdk.org/show_bug.cgi?id=1385
Bug ID: 1385
Summary: rt_bitops.h fails to give implied atomicity guarantees
Product: DPDK
Version: 23.11
Hardware: All
OS: All
Status: UNCONFIRMED
Severity: norm
On Mon, Feb 26, 2024 at 04:51:25AM +, Pavan Nikhilesh Bhagavatula wrote:
> > Make some textual improvements to the introduction to eventdev and event
> > devices in the eventdev header file. This text appears in the doxygen
> > output for the header file, and introduces the key concepts, for
>
Disable use_va flag for VDPA backend type and fixes the issues
with shadow control command processing, when it is disabled.
This will help to make virtio user driver works in IOVA
as PA mode for vDPA backend.
Signed-off-by: Srujana Challa
---
drivers/net/virtio/virtio_ring.h | 12 ++
Hi,
> -Original Message-
> From: Itamar Gozlan
> Sent: Sunday, February 18, 2024 7:11 AM
> To: Itamar Gozlan ; Erez Shitrit ;
> Hamdan Agbariya ; Yevgeny Kliteynik
> ; Slava Ovsiienko ; NBU-
> Contact-Thomas Monjalon (EXTERNAL) ; Suanming
> Mou ; Dariusz Sosnowski
> ; Ori Kam ; Matan Azra
There are use cases where a SA should be able to use different cryptodevs on
different lcores, for example there can be cryptodevs with just 1 qp per VF.
For this purpose this patch relaxes the check in create lookaside session
function.
Also add a check to verify that a CQP is available for the c
On 2/25/2024 6:16 AM, Kumara Parameshwaran wrote:
> If there are no packets flushed in GRO heavy weight mode,
> return false as this fall through code would return true
> indicating that packets are available
>
> Fixes: 461c287ab553 ("app/testpmd: fix GRO packets flush on timeout")
> Cc: sta...@dp
Hello,
On 2/22/24 19:05, Chautru, Nicolas wrote:
Hi Maxime,
Why would we change this here and now? Is the intent not to use new suggested
semantics for new patches only?
The pull request was rejected because of the use of such barrier, which
is reported by checkpatch.
### [PATCH] baseband
On Fri, Feb 23, 2024 at 11:03:36AM -0800, Tyler Retzlaff wrote:
> The current location used for __rte_aligned(a) for alignment of types
> and variables is not compatible with MSVC. There is only a single
> location accepted by both toolchains.
>
> For variables standard C11 offers alignas(a) suppo
Disable use_va flag for VDPA backend type and fixes the issues
with shadow control command processing, when it is disabled.
This will help to make virtio user driver works in IOVA
as PA mode for vDPA backend.
Signed-off-by: Srujana Challa
---
drivers/net/virtio/virtio_ring.h | 12 ++
The current implementation of mlx5_dev_interrupt_nl_cb routine first
compares if event netlink if_index belongs to the same device.
This is not fully correct for the bonding device since the bonding
master and slave interface netlink events indicate the bonding link
status change as well. Add check
Hi,
> -Original Message-
> From: Gregory Etelson
> Sent: Monday, February 12, 2024 3:59 PM
> To: dev@dpdk.org
> Cc: Gregory Etelson ; Maayan Kashani
> ; Dariusz Sosnowski
> Subject: [PATCH v3 0/2] net/mlx5: update pattern validations
>
> PMD updates `rte_errno` if pattern template vali
> MSVC __declspec(align(#)) is limited and accepts only integer literals
> as opposed to constant expressions. define XMM_SIZE to be 16 instead of
> sizeof(xmm_t) and static_assert that sizeof(xmm_t) == 16 for
> compatibility.
>
> Signed-off-by: Tyler Retzlaff
> Acked-by: Morten Brørup
> ---
>
> Uninitialized mbufs are enqueued to eventdev which causes segfault
> on freeing the mbuf in tx adapter.
> Fixed by initializing mbufs before enqueuing to eventdev.
>
> Fixes: 46cf97e4bbfa ("eventdev: add test for eth Tx adapter")
>
> Signed-off-by: Ganapati Kundapura
Acked-by: Pavan Nikhilesh
This patchset adds a new QAT LCE device.
The device currently only supports symmetric crypto,
and only the AES-GCM algorithm.
v2:
- Renamed device from GEN 5 to GEN LCE.
- Removed unused code.
- Updated macro names.
Nishikant Nayak (4):
common/qat: add files specific to GEN LCE
commo
Adding GEN5 files for handling GEN LCE specific operaions.
These files are inherited from the existing files/APIs
which has some changes specific GEN5 requirements
Also updated the mailmap file.
Signed-off-by: Nishikant Nayak
---
v2:
- Renamed device from GEN 5 to GEN LCE.
- Removed unuse
Adding GEN LCE specific macros which is required for updating
the support for GEN LCE features.
Also this patch adds other macros which is being used by GEN LCE
Specific APIs.
Signed-off-by: Nishikant Nayak
---
v2:
- Renamed device from GEN 5 to GEN LCE.
- Removed unused code.
- Updat
This patch handles the changes required for updating the common
header fields specific to GEN LCE, Also added/updated of the response
processing APIs based on GEN LCE requirement.
Signed-off-by: Nishikant Nayak
---
v2:
- Renamed device from GEN 5 to GEN LCE.
- Removed unused code.
- U
Adding one new unit test code for validating the features
added as part of GCM with 64 byte AAD.
The new test case adds one new test for GCM algo for both
encrypt and decrypt operations.
Signed-off-by: Nishikant Nayak
---
v2:
- Removed unused code.
- Added one new unit test, AAD with GCM
From: Hamdan Igbaria
Add support for compare matcher, this matcher will allow
direct comparison between two packet fields, or a packet
field and a value, with fully masked DW.
For now this matcher hash table is limited to size 1x1,
thus it supports only 1 rule STE.
Signed-off-by: Hamdan Igbaria
Add support to use "RTE_FLOW_ITEM_TYPE_COMPARE" with
"RTE_FLOW_FIELD_RAMDOM" as an argument.
The random field is supported only when base is an immediate value,
random field cannot be compared with enother field.
Signed-off-by: Michael Baum
Acked-by: Suanming Mou
---
doc/guides/nics/mlx5.rst
Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field.
Signed-off-by: Michael Baum
Acked-by: Suanming Mou
---
doc/guides/nics/mlx5.rst | 1 +
drivers/net/mlx5/hws/mlx5dr_definer.c | 22 --
drivers/net/mlx5/mlx5_flow_hw.c | 3 +++
3 files c
Add HWS support for compare item with:
- "RTE_FLOW_FIELD_TAG".
- "RTE_FLOW_FIELD_NETA".
- "RTE_FLOW_FIELD_VALUE".
Add HWS + PMD support for compare item with:
- "RTE_FLOW_FIELD_RANDOM".
- "RTE_FLOW_FIELD_ESP_SEQ_NUM".
v2:
- Rebase.
- Add "RTE_FLOW_FIELD_META" compare support.
- Reduce the "Dep
From: Hamdan Igbaria
Add support for compare matcher, this matcher will allow
direct comparison between two packet fields, or a packet
field and a value, with fully masked DW.
For now this matcher hash table is limited to size 1x1,
thus it supports only 1 rule STE.
Signed-off-by: Hamdan Igbaria
Add support to use "RTE_FLOW_ITEM_TYPE_COMPARE" with
"RTE_FLOW_FIELD_RAMDOM" as an argument.
The random field is supported only when base is an immediate value,
random field cannot be compared with enother field.
Signed-off-by: Michael Baum
Acked-by: Suanming Mou
---
doc/guides/nics/mlx5.rst
Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field.
Signed-off-by: Michael Baum
Acked-by: Suanming Mou
---
doc/guides/nics/mlx5.rst | 1 +
drivers/net/mlx5/hws/mlx5dr_definer.c | 22 --
drivers/net/mlx5/mlx5_flow_hw.c | 3 +++
3 files c
Add HWS support for compare item with:
- "RTE_FLOW_FIELD_TAG".
- "RTE_FLOW_FIELD_NETA".
- "RTE_FLOW_FIELD_VALUE".
Add HWS + PMD support for compare item with:
- "RTE_FLOW_FIELD_RANDOM".
- "RTE_FLOW_FIELD_ESP_SEQ_NUM".
v2:
- Rebase.
- Add "RTE_FLOW_FIELD_META" compare support.
- Reduce the "Dep
>
> The current location used for __rte_aligned(a) for alignment of types
> and variables is not compatible with MSVC. There is only a single
> location accepted by both toolchains.
>
> For variables standard C11 offers alignas(a) supported by conformant
> compilers i.e. both MSVC and GCC.
>
>
> >>> TSO breaks when MSS spans more than 8 data fragments. Those
> >>> packets will be dropped by Tx preparation API, but it will
> >>> cause
> >>> MDD event if txonly forwarding engine does not call the Tx
> > preparation
> >>> API before transmitting packets.
> >>>
> >>
Added performance test support for DMA adapter.
Signed-off-by: Amit Prakash Shukla
---
app/test-eventdev/evt_common.h | 3 +
app/test-eventdev/evt_main.c | 15 ++
app/test-eventdev/evt_options.c | 28 +++
app/test-eventdev/evt_options.h | 12 ++
app/test-eventdev/evt
Series-acked-by: Kai Ji
From: Power, Ciara
Sent: 23 February 2024 15:12
To: dev@dpdk.org
Cc: gak...@marvell.com ; Ji, Kai ;
Kusztal, ArkadiuszX ; Power, Ciara
Subject: [PATCH v2 0/4] add new QAT gen3 and gen5
This patchset adds support for two new QAT device
Since now Inline IPsec in cn9k is using same opcode as LA,
remove the definitions of fast path opcode.
Also fix devarg handling for ipsec_out_max_sa to allow 32-bit.
Fixes: fe5846bcc076 ("net/cnxk: add devargs for min-max SPI")
Signed-off-by: Nithin Dabilpuram
---
v5:
- Fixed commit messages an
Define inbound and outbound IPsec data type for PMD API's
rte_pmd_cnxk_hw_sa_read() and rte_pmd_cnxk_hw_sa_write().
Signed-off-by: Nithin Dabilpuram
---
drivers/net/cnxk/cn10k_ethdev_sec.c | 18 +-
drivers/net/cnxk/rte_pmd_cnxk.h | 397 +++-
2 files changed, 411 inse
Add transport mode to security capabilities since it
is supported by UCODE.
Signed-off-by: Nithin Dabilpuram
---
drivers/net/cnxk/cn9k_ethdev_sec.c | 33 ++
1 file changed, 33 insertions(+)
diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c
b/drivers/net/cnxk/cn9k_ethd
From: Satha Rao
New API to dump detailed SQ entries.
Signed-off-by: Satha Rao
---
drivers/common/cnxk/roc_nix.h | 2 +
drivers/common/cnxk/roc_nix_debug.c | 172
drivers/common/cnxk/version.map | 1 +
3 files changed, 175 insertions(+)
diff --git a/d
From: Satha Rao
New API to dump selected descriptor entries from SQE list.
Signed-off-by: Satha Rao
---
drivers/net/cnxk/cnxk_ethdev.c | 1 +
drivers/net/cnxk/cnxk_ethdev.h | 2 ++
drivers/net/cnxk/cnxk_ethdev_ops.c | 10 ++
3 files changed, 13 insertions(+)
diff --git a/dri
In case where cnxk_nix_mtu_set() is called before
data->min_rx_buf_size is set, use buf size from first RQ's
mempool.
Fixes: 34b46320f446 ("net/cnxk: perform early MTU setup for event mode")
Cc: sta...@dpdk.org
Signed-off-by: Nithin Dabilpuram
---
drivers/net/cnxk/cnxk_ethdev_ops.c | 25 +++
Skip setting Tx MTU separately as now the Tx credit configuration
is based on max MTU possible for that link.
Also init MTU with max value for that port.
Fixes: 8589ec212e80 ("net/cnxk: support MTU set")
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/roc_nix.c | 2 +-
drivers/co
From: Sunil Kumar Kori
Device can support maximum frame size up to 9212 bytes. While configuring
mtu, overhead is considered as ethernet header size, crc and
2 * (vlan tags) which translates to 26 bytes.
Exposed overhead to the user via rte_eth_dev_info() is 18 bytes which were
leading to set wr
From: Kommula Shiva Shankar
This patch updates queue entries copy in reta table
based on data type.
Fixes: 1bf6746e653b ("common/cnxk: support NIX RSS")
Signed-off-by: Kommula Shiva Shankar
---
drivers/common/cnxk/roc_nix_rss.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff -
Indirect mbuf can be pointing to data from different pool. Use the right
aura in NIX send header in SG2 and SG case.
Fixes: 862e28128707 ("net/cnxk: add vector Tx for CN9K")
Fixes: f71b7dbbf04b ("net/cnxk: add vector Tx for CN10K")
Fixes: 7e95c11df4f1 ("net/cnxk: add multi-segment Tx for CN9K")
Fi
From: Rahul Bhansali
Fix missing check cookies with multi-seg offload case
Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K")
Cc: sta...@dpdk.org
Signed-off-by: Rahul Bhansali
---
drivers/net/cnxk/cn10k_tx.h | 21 -
1 file changed, 20 insertions(+), 1 deletio
IO attribute is needed to mbox structs to avoid unaligned or pair
access causing by compiler optimization. Add them to structs
where it is missing.
Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response definitions")
Fixes: ddf955d3917e ("common/cnxk: support CPT second pass")
Cc: sta...
Use SQ enable and disable API in TM setup to affect
the state change. This is needed since now SQ state
helps in avoiding multiple SQ enables / SQ disables
if the SQ is already in that state. Otherwise multiple
mbox messages slows down bootup / teardown.
Signed-off-by: Nithin Dabilpuram
---
driv
From: Rahul Bhansali
Currently in debug mode when a buffer is allocated in SW,
nb_segs will have invalid values as it didn't come from driver
Rx path. Hence reset mbuf next and nb_segs fields in multi-seg Tx path.
Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K")
Signed-off-by: R
This patch-set adds support of encapsulation level for HWS modify field
in MLX5 PMD.
Outermost is represented by 0,1 and inner is represented by 2.
In addition, modify inner/outer us added for both IPv6 flow label and
IPv6 traffic class.
v2:
- Rebase.
- Add "copy from inner" to release notes.
v3:
The "mlx5_modification_field" enumeration has 2 different fields
representing the same value 0x4A.
1. "MLX5_MODI_OUT_IPV6_NEXT_HDR" - specific for IPv6.
2. "MLX5_MODI_OUT_IP_PROTOCOL" - for both IPv4 and IPv6.
This patch removes "MLX5_MODI_OUT_IPV6_NEXT_HDR" and replaces all its
usages with "MLX
This patch adds inner values into PRM modify field list for each
existing outer field.
Signed-off-by: Michael Baum
Acked-by: Dariusz Sosnowski
---
drivers/common/mlx5/mlx5_prm.h | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/
Reorder modification field PRM list according to values from lowest to
highest.
This patch also removes value specification from all fields which their
value is one more than previous one.
Signed-off-by: Michael Baum
Acked-by: Dariusz Sosnowski
---
drivers/common/mlx5/mlx5_prm.h | 32 ++
Add IPv6 flow label field into PRM modify field list.
The new values are "MLX5_MODI_OUT_IPV6_FLOW_LABEL" and
"MLX5_MODI_IN_IPV6_FLOW_LABEL".
Signed-off-by: Michael Baum
Acked-by: Dariusz Sosnowski
---
drivers/common/mlx5/mlx5_prm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/c
This patch adds support for copying from inner fields using "level" 2.
Signed-off-by: Michael Baum
Acked-by: Dariusz Sosnowski
---
doc/guides/nics/mlx5.rst | 28 +-
doc/guides/rel_notes/release_24_03.rst | 1 +
drivers/net/mlx5/mlx5_flow.c | 12 ++-
drivers/net/m
Add HW steering support for IPv6 traffic class field modification.
Copy from inner IPv6 traffic class field is also supported using
"level=2".
Signed-off-by: Michael Baum
Acked-by: Dariusz Sosnowski
---
doc/guides/rel_notes/release_24_03.rst | 1 +
drivers/net/mlx5/mlx5_flow_dv.c| 11 +
Add HW steering support for IPv6 flow label field modification.
Copy from inner IPv6 flow label field is also supported using "level=2".
Signed-off-by: Michael Baum
Acked-by: Dariusz Sosnowski
---
doc/guides/rel_notes/release_24_03.rst | 1 +
drivers/net/mlx5/mlx5_flow_dv.c| 12 +++
> > >>> TSO breaks when MSS spans more than 8 data fragments. Those
> > >>> packets will be dropped by Tx preparation API, but it will
> > >>> cause
> > >>> MDD event if txonly forwarding engine does not call the Tx
> > > preparation
> > >>> API before transmitting packets.
> >
Reviewed-by: Jeremy Spewock
On 2/26/2024 1:44 AM, Chaoyong He wrote:
> From: Long Wu
>
> Add a function to check if a device is representor port, also
> modified the related codes for PMDs.
>
> Signed-off-by: Long Wu
> Reviewed-by: Chaoyong He
> Reviewed-by: Peng Zhang
>
Reviewed-by: Ferruh Yigit
On 2/26/2024 1:44 AM, Chaoyong He wrote:
> This patch series add the support of MARK and RSS flow action for NFP
> PMD, also add a new function to help check if a device is representor
> port.
>
> ---
> v2:
> * Modify the title and description of patch series to make it more
> clear.
> * Add a ne
> From: Jerin Jacob [mailto:jerinjac...@gmail.com]
> Sent: Monday, 26 February 2024 09.34
>
> On Fri, Feb 23, 2024 at 7:30 PM Morten Brørup
> wrote:
> >
> > Bugfix: The vlan in the bulletin does not contain a VLAN header, only
> the
> > VLAN ID, so only copy 2 byte, not 4. The target structure ha
On Mon, Feb 19, 2024 at 11:52 AM Thomas Monjalon wrote:
>
> 05/12/2023 10:45, David Marchand:
> > +#define VHOST_USER_ASSERT_LOCK(dev, vq, id) do { \
> > + RTE_BUILD_BUG_ON(!vhost_message_handlers[id].lock_all_qps); \
> > + vq_assert_lock(dev, vq); \
> > +} while (0)
>
> Since "eal: enhanc
On 2/26/2024 3:16 AM, Jie Hai wrote:
> On 2024/2/23 21:53, Ferruh Yigit wrote:
>> On 2/20/2024 3:58 AM, Jie Hai wrote:
>>> Hi, Ferruh,
>>>
>>> Thanks for your review.
>>>
>>> On 2024/2/7 22:15, Ferruh Yigit wrote:
On 2/6/2024 1:10 AM, Jie Hai wrote:
> From: Dengdui Huang
>
> When
A simple comment in vhost_user_msg_handler() is not that robust.
Add a lock_all_qps property to message handlers so that their
implementation can add a build check and assert a vq is locked.
Signed-off-by: David Marchand
---
Changes since v2:
- dropped review tags,
- following use of static_asse
This patchset adds support for two new QAT devices.
A new GEN3 device, and a GEN5 device, both of which have
wireless slice support for algorithms such as ZUC-256.
Symmetric, asymmetric and compression are all supported
for these devices.
v3:
- Modified year in licence tag of new gen5 files.
v2
Add new gen3 QAT device ID.
This device has a wireless slice, but other gen3 devices do not, so we
must set a flag to indicate this wireless enabled device.
Capabilities for the device are slightly different from base gen3
capabilities, some are removed from the list for this device.
Symmetric, a
The new gen3 device handles wireless algorithms on wireless slices,
based on the device wireless slice support, set the required flags for
these algorithms to move slice.
One of the algorithms supported for the wireless slices is ZUC 256,
support is added for this, along with modifying the capabil
The new QAT GEN3 device uses new macros for CMAC values, rather than
using XCBC_MAC ones.
The wireless slice handles CMAC in the new gen3 device, and no key
precomputes are required by SW.
Signed-off-by: Ciara Power
Acked-by: Kai Ji
---
drivers/common/qat/qat_adf/icp_qat_hw.h | 4 +++-
driver
Add new gen5 QAT device ID.
This device has a wireless slice, so we must set a flag to indicate
this wireless enabled device.
Asides from the wireless slices and some extra capabilities for
wireless algorithms, the device is functionally the same as gen4 and can
reuse most functions and macros.
Sy
On Mon, Feb 26, 2024 at 12:51:38PM +, Konstantin Ananyev wrote:
>
>
> > MSVC __declspec(align(#)) is limited and accepts only integer literals
> > as opposed to constant expressions. define XMM_SIZE to be 16 instead of
> > sizeof(xmm_t) and static_assert that sizeof(xmm_t) == 16 for
> > compa
On Mon, Feb 26, 2024 at 01:23:35PM +, Konstantin Ananyev wrote:
>
>
> >
> > The current location used for __rte_aligned(a) for alignment of types
> > and variables is not compatible with MSVC. There is only a single
> > location accepted by both toolchains.
> >
> > For variables standard C1
On Sat, Feb 24, 2024 at 12:16:58PM +0100, Morten Brørup wrote:
> Hi Tyler,
>
> Does MSVC permit empty structures, i.e. structures with no fields? Perhaps
> with some additional decoration, a la [[msvc::no_unique_address]].
> If so, perhaps that would be a possible workaround for RTE_MARKERs.
i h
23/02/2024 00:46, Tyler Retzlaff:
> Providing a custom prefix when logging is common for components. Lift
> ISO C99 compliant helper macros from mlx5_common.h and provide
> RTE_LOG_LINE_PREFIX macro that can expand similar to RTE_LOG_LINE with
> a custom prefix and argument list.
[...]
> > +#define
On Sat, 24 Feb 2024 11:58:59 +0100
Thomas Monjalon wrote:
> 24/02/2024 09:21, Tyler Retzlaff:
> > Update prefetch inline functions to access rte_mbuf struct fields
> > directly instead of via cacheline{0,1} marker extension fields.
> >
> > Signed-off-by: Tyler Retzlaff
> [...]
> > rte_mbuf_p
MSVC __declspec(align(#)) is limited and accepts only integer literals
as opposed to constant expressions. define XMM_SIZE to be 16 instead of
sizeof(xmm_t) and static_assert that sizeof(xmm_t) == 16 for
compatibility.
Signed-off-by: Tyler Retzlaff
Acked-by: Morten Brørup
---
lib/eal/x86/includ
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.
For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.
For types the standa
1 - 100 of 188 matches
Mail list logo
