Hi Ramkumar,
> -Original Message-
> From: Ramkumar Balu
> Sent: Monday, November 29, 2021 10:52 AM
> To: Akhil Goyal ; Anoob Joseph ;
> Doherty, Declan ; Zhang, Roy Fan
> ; Ankur Dwivedi ; Tejasree
> Kondoj
> Cc: sta...@dpdk.org; dev@dpdk.org; Ramkumar
> Subject: [PATCH 0/5] cryptodev:
> -Original Message-
> From: Ramkumar Balu
> Sent: Monday, November 29, 2021 10:52 AM
> To: Akhil Goyal ; Anoob Joseph ;
> Doherty, Declan ; Zhang, Roy Fan
> ; Ankur Dwivedi ; Tejasree
> Kondoj
> Cc: sta...@dpdk.org; dev@dpdk.org; Ramkumar
> Subject: [PATCH 2/5] crypto/openssl: fix ou
v2-change-log
* using dev args for both DPAA1 and DPAA2 drivers to
dump debug prints on sec error.
Akhil Goyal (1):
crypto/dpaa2_sec: support AES-GMAC
Franck LENORMAND (1):
common/dpaax: caamflib: Remove code related to SEC ERA 1 to 7
Gagandeep Singh (3):
common/dpaax: change job processi
For PDCP SDAP test cases, HW sec engine process the
jobs in WAIT mode.
Signed-off-by: Gagandeep Singh
---
drivers/common/dpaax/caamflib/desc/sdap.h | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/common/dpaax/caamflib/desc/sdap.h
b/drivers/comm
From: Franck LENORMAND
DPAA1 and DPAA2 platforms use SEC ERA 8 and 10 only.
This patch removes code in SDAP and PDCP header related to these
ERA to simplify the codebase:
- Simplify logic using RTA_SEC_ERA_<> macro
- Remove era_2_sw_hfn_ovrd dedicated to RTA_SEC_ERA_2
Signed-off-by: Franck LE
From: Nipun Gupta
This patch supports ordered queue for DPAA2 platform.
Signed-off-by: Nipun Gupta
---
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 255 +++-
drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 8 +-
drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h| 14 +-
3 files cha
From: Akhil Goyal
This patch supports AES_GMAC algorithm for DPAA2
driver.
Signed-off-by: Akhil Goyal
Signed-off-by: Gagandeep Singh
---
doc/guides/cryptodevs/features/dpaa2_sec.ini | 1 +
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 14 -
drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
From: Hemant Agrawal
Change the digest size to supported value by the HW engine.
Signed-off-by: Hemant Agrawal
---
drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
b/drivers/crypto/dpaa2
Few useful debug prints added in dequeue function.
Signed-off-by: Gagandeep Singh
---
doc/guides/cryptodevs/dpaa2_sec.rst | 10 ++
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 136 +++-
2 files changed, 144 insertions(+), 2 deletions(-)
diff --git a/doc/guides/cryptode
From: Hemant Agrawal
This patch add more checks on next type for PDCP cases.
Fixes: 45e019608f31 ("crypto/dpaa2_sec: support integrity only PDCP")
Fixes: a1173d55598c ("crypto/dpaa_sec: support PDCP offload")
Cc: sta...@dpdk.org
Signed-off-by: Hemant Agrawal
---
drivers/crypto/dpaa2_sec/dpaa2
Adding useful debug prints in DPAA driver for
easy debugging.
Signed-off-by: Gagandeep Singh
---
doc/guides/cryptodevs/dpaa_sec.rst | 10 ++
drivers/bus/dpaa/dpaa_bus.c| 16 ++-
drivers/crypto/dpaa_sec/dpaa_sec.c | 192 -
3 files changed, 213 insertions(+),
When building with -Db_sanitize=thread, GCC gives a warning:
drivers/net/mlx5/mlx5_flow_meter.c: In function ‘mlx5_flow_meter_create’:
drivers/net/mlx5/mlx5_flow_meter.c:1170:33: warning: ‘legacy_fm’ may be
used uninitialized in this function [-Wmaybe-uninitialized]
This is a false-positive:
A debug assertion in Single-Packet Receive Queue (SPRQ) mode
required all Rx mbufs to have a 128 byte headroom,
based on the assumption that rte_pktmbuf_init() sets it.
However, rte_pktmbuf_init() may set a smaller headroom
if the dataroom is insufficient, e.g. this is a natural case
for split buff
This patchset adds following asymmetric crypto algorithms to Intel QuickAssist
Technology driver:
- DSA
- DH
- ECDSA
- ECPM
Arek Kusztal (2):
crypto/qat: refactor asymmetric crypto functions
crypto/qat: add named elliptic curves
.../qat/qat_adf/qat_pke_functionality_arrays.h | 254 -
This patch adds secp256r1 and 521r1 elliptic curves to Intel
QuickAssist Technology PMD.
Signed-off-by: Arek Kusztal
---
drivers/crypto/qat/qat_asym.c | 15
drivers/crypto/qat/qat_ec.h | 203 ++
2 files changed, 218 insertions(+)
create mode 10064
This commit refactors asummetric crypto functions
in Intel QuickAssist Technology PMD.
Functions right now are shorter and far easier readable,
plus it facilitates addition of new algorithms.
Signed-off-by: Arek Kusztal
---
.../qat/qat_adf/qat_pke_functionality_arrays.h | 254 -
drivers
This commit enables CPM2.0b devices in Intel QuickAssist
Technology PMD.
Signed-off-by: Arek Kusztal
---
doc/guides/cryptodevs/qat.rst | 2 ++
doc/guides/rel_notes/release_22_03.rst | 4
drivers/common/qat/qat_device.c| 4
3 files changed, 10 insertions(+)
diff --git
This commit removes OpenSSL 3.0 deprecated functions
from Intel QuickAssist Technology PMD. It does not remove
all deprecated functions, this will be added in later versions.
Signed-off-by: Arek Kusztal
---
drivers/crypto/qat/qat_sym_session.c | 47 ++--
1 file ch
Hi mempool maintainers and DPDK team.
Does anyone know the reason or history why CACHE_FLUSHTHRESH_MULTIPLIER was
chosen to be 1.5? I think it is counterintuitive.
The mempool cache flush threshold was introduced in DPDK version 1.3; it was
not in DPDK version 1.2. The copyright notice for rte_
On Tue, 28 Dec 2021 15:01:20 +0800
Yanling Song wrote:
> On Fri, 24 Dec 2021 09:44:57 -0800
> Stephen Hemminger wrote:
>
> > On Fri, 24 Dec 2021 16:32:18 +0800
> > Yanling Song wrote:
> >
> > > The patchsets introduce SPNIC driver for Ramaxel's SPNxx serial NIC
> > > cards into DPDK 22.03.
On Fri, 24 Dec 2021 16:32:23 +0800
Yanling Song wrote:
> +static void nic_event_handler(void *hwdev
This is one example of something this driver does a lot.
It casts away the hardware device structure to void * then reassigns it to the
the hardware structure. This is the classic type unsafe C s
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