On Wed, Mar 31, 2021 at 3:00 PM wrote:
>
> From: Pavan Nikhilesh
>
> In traditional event programming model, events are identified by a
> flow-id and a uintptr_t. The flow-id uniquely identifies a given event
> and determines the order of scheduling based on schedule type, the
> uintptr_t holds a
On Wed, Mar 31, 2021 at 1:06 AM Timothy McDaniel
wrote:
>
> This patch series adds support for DLB v2.5 to
> the current DLB V2.0 PMD. The resulting PMD supports
> both hardware versions.
>
> The main differences between the DLB v2.5 and v2.0 hardware
> are:
> - Number of queues/ports
> - DLB v2.5
On Wed, Mar 31, 2021 at 1:07 AM Timothy McDaniel
wrote:
>
> This commit adds support for DLB v2.5 probe-time hardware init,
> and sets up a framework for incorporating the remaining
> changes required to support DLB v2.5.
>
> DLB v2.0 and DLB v2.5 are similar in many respects, but their
> register
> -Original Message-
> From: Shijith Thotton
> Sent: Friday, April 2, 2021 10:31 PM
> To: dev@dpdk.org
> Cc: Shijith Thotton ; tho...@monjalon.net;
> jer...@marvell.com; Gujjar, Abhinandan S ;
> hemant.agra...@nxp.com; nipun.gu...@nxp.com;
> sachin.sax...@oss.nxp.com; ano...@marvell.com
On Wed, Mar 17, 2021 at 3:50 AM Timothy McDaniel
wrote:
>
> Update domain creation logic to account for DLB v2.5
> credit scheme, new register map, and new register access
> macros.
>
> Signed-off-by: Timothy McDaniel
> ---
> drivers/event/dlb2/dlb2_user.h| 13 +-
> drivers/eve
On Wed, Mar 31, 2021 at 1:08 AM Timothy McDaniel
wrote:
>
> Updated low level hardware functions to account for new
> register map and hardware access macros.
>
> Signed-off-by: Timothy McDaniel
> ---
> drivers/event/dlb2/pf/base/dlb2_resource.c| 213 --
> .../event/dlb2/pf/b
On Wed, Mar 31, 2021 at 1:09 AM Timothy McDaniel
wrote:
>
> The file dlb_resource_new.c now contains all of the low level
> functions required to support both DLB v2.0 and DLB v2.5, and
> the original file (dlb_resource.c) was removed in the previous
> commit, so rename dlb_resource_new.c to dlb_r
I would like to change my email to personal email address.
Signed-off-by: Liang Ma
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0ec558854..bca79c52b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1237,7 +1237,7 @@ F: drivers/
On Wed, Mar 31, 2021 at 1:09 AM Timothy McDaniel
wrote:
>
> Updated eventdev device name to be dlb_event instead of
> dlb2_event. The new name will be used for all versions
> of the DLB hardware. This change required corresponding changes
> to the the directory name that contains the PMD, as well
> -Original Message-
> From: Shijith Thotton
> Sent: Friday, April 2, 2021 10:31 PM
> To: dev@dpdk.org
> Cc: Shijith Thotton ; tho...@monjalon.net;
> jer...@marvell.com; Gujjar, Abhinandan S ;
> hemant.agra...@nxp.com; nipun.gu...@nxp.com;
> sachin.sax...@oss.nxp.com; ano...@marvell.com
On Thu, Apr 1, 2021 at 6:08 PM Nithin Dabilpuram
wrote:
>
> This patchset adds initial support for common code for
> Marvell CN10K SoC. Based on this common 'cnxk' driver, new PMD's
> such as 'net/cnxk', 'mempool/cnxk', 'event/cnxk' etc, will be added
> later on.
>
> Initially 'cnxk' drivers will
> -Original Message-
> From: Shijith Thotton
> Sent: Friday, April 2, 2021 10:31 PM
> To: dev@dpdk.org
> Cc: Akhil Goyal ; tho...@monjalon.net;
> jer...@marvell.com; Gujjar, Abhinandan S ;
> hemant.agra...@nxp.com; nipun.gu...@nxp.com;
> sachin.sax...@oss.nxp.com; ano...@marvell.com; ma
This patchset adds the mempool/cnxk driver which provides the support for the
integrated mempool device found in Marvell CN10K SoC.
The code includes mempool driver functionality for Marvell CN9K SoC as well,
but right now it is not enabled. The future plan is to deprecate existing
mempool/octeont
Add the implementation for CNXk mempool device
probe and remove.
Signed-off-by: Pavan Nikhilesh
Signed-off-by: Ashwin Sekhar T K
---
doc/guides/mempool/cnxk.rst | 23 +
drivers/mempool/cnxk/cnxk_mempool.c | 131 +++-
2 files changed, 150 insertions(+), 4 del
Add generic CNXk mempool ops which will enqueue/dequeue
from pool one element at a time.
Signed-off-by: Pavan Nikhilesh
Signed-off-by: Ashwin Sekhar T K
---
drivers/mempool/cnxk/cnxk_mempool.h | 26
drivers/mempool/cnxk/cnxk_mempool_ops.c | 171
drivers/mempoo
Add the meson based build infrastructure for Marvell
CNXK mempool driver along with stub implementations
for mempool device probe.
Also add Marvell CNXK mempool base documentation.
Signed-off-by: Pavan Nikhilesh
Signed-off-by: Jerin Jacob
Signed-off-by: Nithin Dabilpuram
Signed-off-by: Ashwin
Register the CNXk mempool lf init/fini callbacks which
will set the appropriate mempool ops to be used according
to the platform.
Signed-off-by: Ashwin Sekhar T K
---
drivers/mempool/cnxk/cnxk_mempool_ops.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/mempoo
Add Marvell CN9k mempool ops and implement CN9k mempool
alloc which makes sure that the element size always occupy
odd number of cachelines to ensure even distribution among
of elements among L1D cache sets.
Signed-off-by: Pavan Nikhilesh
Signed-off-by: Ashwin Sekhar T K
---
drivers/mempool/cnx
Add Marvell CN9k mempool enqueue/dequeue. Marvell CN9k
supports burst dequeue which allows to dequeue up to 32
pointers using pipelined casp instructions.
Signed-off-by: Pavan Nikhilesh
Signed-off-by: Ashwin Sekhar T K
---
doc/guides/mempool/cnxk.rst | 4 +++
drivers/mempool/cnxk/c
Add Marvell CN10k mempool ops and implement CN10k mempool alloc.
CN10k has 64 bytes L1D cache line size. Hence the CN10k mempool
alloc does not make the element size an odd multiple L1D cache
line size as NPA requires the element sizes to be multiples of
128 bytes.
Signed-off-by: Ashwin Sekhar T
Marvell CN10k mempool supports batch enqueue/dequeue which can
dequeue up to 512 pointers and enqueue up to 15 pointers using
a single instruction.
These batch operations require a DMA memory to enqueue/dequeue
pointers. This patch adds the initialization of this DMA memory.
Signed-off-by: Ashwin
Add the implementation for Marvell CN10k mempool batch enqueue op.
Signed-off-by: Ashwin Sekhar T K
---
drivers/mempool/cnxk/cn10k_mempool_ops.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c
b/drivers/mempoo
Add the implementation for Marvell CN10k get count op.
Signed-off-by: Ashwin Sekhar T K
---
drivers/mempool/cnxk/cn10k_mempool_ops.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c
b/drivers/mempool/cnxk/cn10k
Add the implementation for Marvell CN10k mempool batch dequeue op.
Signed-off-by: Ashwin Sekhar T K
---
drivers/mempool/cnxk/cn10k_mempool_ops.c | 72 +++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c
b/drivers/mempoo
On Sat, Apr 3, 2021 at 7:49 PM Ashwin Sekhar T K wrote:
>
> Add the implementation for Marvell CN10k mempool batch enqueue op.
>
> Signed-off-by: Ashwin Sekhar T K
> ---
> drivers/mempool/cnxk/cn10k_mempool_ops.c | 28 +++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
On Sat, Apr 3, 2021 at 7:49 PM Ashwin Sekhar T K wrote:
>
> Marvell CN10k mempool supports batch enqueue/dequeue which can
> dequeue up to 512 pointers and enqueue up to 15 pointers using
> a single instruction.
>
> These batch operations require a DMA memory to enqueue/dequeue
> pointers. This pa
On Windows, EAL contains two sets of functions and macros for POSIX
compatibility: and a networking shim (socket headers).
The latter conflicts with system headers and should not exist.
Exposing the former from EAL can break consumer own POSIX compatibility
layer and is against standards in genera
POSIX sleep(3) is missing from Windows.
Add generic rte_thread_sleep() to suspend current OS thread.
Signed-off-by: Dmitry Kozlyuk
Acked-by: Khoa To
Acked-by: Ray Kinsella
---
lib/librte_eal/common/eal_common_timer.c | 5 +++--
lib/librte_eal/include/rte_thread.h | 11 +++
lib/li
Make asprintf(3) implementation for Windows private to EAL, so that it's
hidden from external consumers. It is not exposed to internal consumers
either, because they don't need asprintf() and also because callers from
other modules would have no reliable way to free allocated memory.
Signed-off-by
DPDK code often relies on functions and macros that are not standard C,
but are found on all platforms, even if by slightly different names.
Windows provided macros or inline definitions for such symbols.
However, when placed in public header, these symbols were unnecessarily
exposed, breaking con
Windows Sockets headers contain `#define s_addr S_un.S_addr`, which
conflicts with definition of `s_addr` field of `struct rte_ether_hdr`.
Prieviously `s_addr` was undefined in , which had been
breaking access to `s_addr` field of `struct in_addr`, so some DPDK
and Windows headers could not be incl
Users of relied on it to provide IP-related defines,
like IPPROTO_* constants, but still had to include POSIX headers
for inet_pton() and other standard IP-related facilities.
Extend so that it is a single header to gain access
to IP-related facilities on any OS. Use it to replace POSIX includes
Hi guys,
> > > In many usage scenarios input mbufs for rte_sched_port_enqueue() are
> > not
> > > yet in the CPU cache(s). That causes quite significant stalls due to
> > > memory
> > > latency. Current implementation tries to migitate it using SW pipeline and
> > SW
> > > prefetch techniques,
2021-04-01 13:27 (UTC+0100), Nick Connolly:
[...]
> +def copy_pmd_files(pattern, to_dir):
> + for file in glob.glob(os.path.join(pmd_dir, pattern)):
> + to = os.path.join(to_dir, os.path.basename(file))
> + shutil.copy2(file, to)
> + print(to + ' -> ' + file)
2021-03-26 09:22 (UTC+0100), Gabriel Ganne:
> libpcap is already found and registered as a dependency by meson, and
> the dependency is already correctly used in librte_port. This line is
> just unnecessary.
>
> It also has the side effect of messing with the meson link line: dpdk
> link will be d
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