On 12/24/2018 8:31 PM, Ananyev, Konstantin wrote:
>
>> -Original Message-
>> From: Akhil Goyal [mailto:akhil.go...@nxp.com]
>> Sent: Monday, December 24, 2018 1:50 PM
>> To: Ananyev, Konstantin ; dev@dpdk.org
>> Cc: Nicolau, Radu ; Awal, Mohammad Abdul
>> ; Iremonger, Bernard
>>
>> Subj
Few fixes and minor enhancements in NXP DPAA driver
Hemant Agrawal (4):
bus/dpaa: fix the logical to physical core affine logic
net/dpaa: fix the secondary process
net/dpaa: update supported ptypes
net/dpaa: update RSS offload types
drivers/bus/dpaa/dpaa_bus.c| 41 +--
The code was treating the lcore id as physical core id.
The code is updated to use actual physical core value
for any core affinity logic.
Note that DPAA devices are single cluster systems.
Fixes: 5d944582d028 ("bus/dpaa: check portal presence in the caller function")
Cc: Nipun Gupta
Cc: sta...@
Validated and tested additional offload flags for RSS
configuration.
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa/dpaa_ethdev.h | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h
index 2fc723171..
Validated and tested additional packet type for the DPAA
platform.
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa/dpaa_ethdev.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 5448a2ca7..b
In order to support I/O from secondary process, the
burst APIs and OPS APIs shall be mapped/plugged. This
patch fixes the code to remap the ops and burst apis.
Fixes: ff9e112d7870 ("net/dpaa: add NXP DPAA PMD driver skeleton")
Cc: sta...@dpdk.org
Signed-off-by: Hemant Agrawal
---
drivers/net/dp
This patch implements the set of actions to support offload
of packet header modifications to MLX5 NIC.
Implamantation is based on RFC [1].
[1] http://mails.dpdk.org/archives/dev/2018-November/119971.html
Signed-off-by: Dekel Peled
---
v2: Apply code review comments:
* update LIB_GLUE_VERS
In some vendors the RX and TX configuration must be the same, therefore
the MTU size need to be equal to max_rx_pkt_len.
The MTU is the largest size packet in bytes that can be sent on the
network, therefore before changing this parameter, the NIC could not
receive packets larger than 1500 bytes, w
VIRTIO_F_ORDER_PLATFORM is required to use proper memory barriers
in case of HW vhost implementations like vDPA.
DMA barriers (rte_cio_*) are sufficent for that purpose.
Previously known as VIRTIO_F_IO_BARRIER.
Signed-off-by: Ilya Maximets
---
Version 2:
* rebased on current master (packed r
26/12/2018 06:21, Varghese, Vipin:
> HI Thomas,
>
> Snipped
>
> > > > Small nits
> > > > 9th patch in this set is doc. So above info need to be corrected.
> > > > if you are addressing my earlier comment of separating out mempool
> > > > element iteration changes in to separate new patch 9/10 .Pl
snipped
> > > > > Small nits
> > > > > 9th patch in this set is doc. So above info need to be corrected.
> > > > > if you are addressing my earlier comment of separating out
> > > > > mempool element iteration changes in to separate new patch 9/10
> > > > > .Please keep my ack in next version
> > >
When CONFIG_RTE_FORCE_INTRINSICS is enabled for x86, the clang
compilation error was:
include/generic/rte_atomic.h:215:9: error:
implicit declaration of function '__atomic_exchange_2'
is invalid in C99
include/generic/rte_atomic.h:494:9: error:
V3:
1. Implemented the ticket lock to improve the fairness and predictability.
The locks are obtained in the order of requested.
V2:
1. FORCE_INTRINCIS is still an option for ppc/x86, although not is use
by default, so don't remove it from generic file.
2. Fix the clang compiler error on x86
To precisely benchmark the spinlock performance, uses the precise
version of getting timestamps, which enforces the timestamps are
obtained at the expected places.
Signed-off-by: Gavin Hu
Reviewed-by: Phil Yang
---
test/test/test_spinlock.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
The test is to benchmark the performance of spinlock by counting the
number of spinlock acquire and release operations within the specified
time.
A typical pair of lock and unlock operations costs tens or hundreds of
nano seconds, in comparison to this, delaying 1 us outside of the locked
region is
The __sync builtin based implementation generates full memory barriers
('dmb ish') on Arm platforms. Using C11 atomic builtins to generate one way
barriers.
Here is the assembly code of __sync_compare_and_swap builtin.
__sync_bool_compare_and_swap(dst, exp, src);
0x0090f1b0 <+16>:e0
Instead of getting timestamps per iteration, amortize its overhead
can help getting more precise benchmarking results.
Signed-off-by: Gavin Hu
Reviewed-by: Joyce Kong
---
test/test/test_spinlock.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a
From: Joyce Kong
The old implementation is unfair, some threads may take locks aggressively
while leaving the other threads starving for long time. As shown in the
following test, within same period of time, there are threads taking locks
much more times than the others.
The new implementation g
> On Tue, Dec 18, 2018 at 08:30:16PM +0900, Hideyuki Yamashita wrote:
> > > On Tue, Dec 18, 2018 at 02:52:16PM +0900, Hideyuki Yamashita wrote:
> > > > > On Tue, Dec 18, 2018 at 12:11:33PM +0900, Hideyuki Yamashita wrote:
> > > > > >
> > > > > > On Mon, Dec 17, 2018 at 11:21:01AM +, Burakov, A
When RTE_LIBRTE_MBUF_DEBUG enabled, rte_mbuf_sanity_check()
function defined in rte_mbuf.so library,
add it while linking the librte_pmd_ice.so library to fix
the build issue.
error log:
/usr/bin/ld: ice_rxtx.o: in function `ice_recv_pkts':
ice_rxtx.c:(.text+0x1d97): undefined reference to
`rte_mb
The check !dpaa2->cscn is not correct to check non-null value.
Fixes: 5d9a1e4d23fe ("net/dpaa2: enhance queue memory cleanup")
Cc: sta...@dpdk.org
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa2/dpaa2_ethdev.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net
This patch set covers following:
1. Fixes in the existing NXP DPAA2 bus and net pmd
2. New object (DPDMUX) support in NIC driver for better classification
3. Improvements to support secondary process
4. Upgrade the low level QBMAN HW lib
Akhil Goyal (1):
net/dpaa2: enable optional timestamp in
From: Youri Querry
The code was incorrectly using the cache inhibited access.
It shall use cached enabled access for better performance.
Fixes: 293c0ca94c36 ("bus/fslmc: support memory backed portals with QBMAN 5.0")
Cc: sta...@dpdk.org
Signed-off-by: Youri Querry
---
drivers/bus/fslmc/qbman/
Existing code is using the lcore id as the physical core
id. Add code to get the right physical id.
Also, dpaa2 can not support one lcore mapping to multiple cpus,
print err on such cases.
Fixes: ce9efbf5bb09 ("bus/fslmc: support dynamic logging")
Cc: sta...@dpdk.org
Signed-off-by: Hemant Agrawa
From: Sachin Saxena
Uninitialized portal memory is causing unwanted issues.
Fixes: 293c0ca94c36 ("bus/fslmc: support memory backed portals with QBMAN 5.0")
Cc: sta...@dpdk.org
Signed-off-by: Sachin Saxena
---
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 2 ++
1 file changed, 2 insertions(+)
di
From: Shreyansh Jain
Current code expects that bus->parse() would get a string containing
the name of the bus. That is incorrect. bus->parse() is expected
to have strings like:
dpni.1,key=val
dpio.2,key=val
when user passed:
-b fslmc:dpni.1,key=val
This commit fixes this behavior.
Fixes:
In order to support I/O from secondary process, the
burst APIs and OPS APIs shall be mapped/plugged.
Fixes: c147eae01cb3 ("net/dpaa2: introduce NXP DPAA2 driver")
Cc: sta...@dpdk.org
Signed-off-by: Shreyansh Jain
---
drivers/net/dpaa2/dpaa2_ethdev.c | 9 -
1 file changed, 8 insertions(+
This patch upgrades and sync the dpdk based qbman code
with new version of qbman flib.
Signed-off-by: Youri Querry
Signed-off-by: Nipun Gupta
Signed-off-by: Hemant Agrawal
---
drivers/bus/fslmc/qbman/qbman_portal.c | 8
drivers/bus/fslmc/qbman/qbman_sys.h| 17 +++--
2
This is just a information. No need to print
it as a error.
Fixes: ce9efbf5bb09 ("bus/fslmc: support dynamic logging")
Cc: sta...@dpdk.org
Signed-off-by: Hemant Agrawal
---
drivers/bus/fslmc/fslmc_vfio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/bus/fslmc/fslmc
From: Akhil Goyal
This patch enables the population of timestamp field
in mbuf on packet receive.
It may give performance impact on LX2xxx platforms.
So, it has been made optional for Lx2xxx platform.
One shall call, rte_dpaa2_enable_ts() to enable it.
Nothing is required for LS2 and LS1088 plat
Add flag in portal init to adjust the qbman memory type,
to decide between legacy portal mode or newly introduced
memory backed portals.
Signed-off-by: Roy Pledge
Signed-off-by: Youri Querry
Signed-off-by: Hemant Agrawal
---
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 2 +
.../bus/fslmc/q
This is to align with the latest qbman hw library
Signed-off-by: Youri Querry
Signed-off-by: Hemant Agrawal
---
drivers/bus/fslmc/qbman/qbman_portal.c | 51 +++---
drivers/bus/fslmc/qbman/qbman_portal.h | 2 +-
2 files changed, 23 insertions(+), 30 deletions(-)
diff --git
It was not required to be a function.
Signed-off-by: Hemant Agrawal
---
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 2 +-
drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
b/drivers/bus/fslmc/po
From: Nipun Gupta
Add support in bus and vfio to scan dpdmux type of objects
Signed-off-by: Nipun Gupta
---
drivers/bus/fslmc/fslmc_bus.c | 5 -
drivers/bus/fslmc/fslmc_vfio.c | 2 ++
drivers/bus/fslmc/rte_fslmc.h | 1 +
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drive
From: Nipun Gupta
dpdmux object is added as a part of net driver as it is used to
de-multiplex packets to separate interfaces on basis of specific rules.
These rules can be configured from the software
Signed-off-by: Nipun Gupta
---
drivers/net/dpaa2/Makefile| 1 +
drivers/net/dp
From: Shreyansh Jain
Previously FSLMC bus only supported blacklisting of DPNI (eth),
DPSECI (crypto) devices. With this patch, devices like DPIO,
DPMCP, and other DP* can also be blacklisted/whitelisted.
This is a required condition for secondary processes where the
secondary needs to be passed
From: Pankaj Chauhan
This is required to map any accelerator memory
and PCI address to VFIO using QDMA.
Signed-off-by: Minghuan Lian
Signed-off-by: Pankaj Chauhan
---
drivers/bus/fslmc/fslmc_vfio.c | 42 +
drivers/bus/fslmc/fslmc_vfio.h | 1 +
dr
From: Shreyansh Jain
The I/O threads for DPAA2 take their reference for bpool ID, the
port ID and other info like qdid, from the rte_eth_dev. Further,
to get this data during I/O operation, a reference of the RTE
device is kept in the queue structure (dpaa2_queue).
In case of secondary processes
From: Nipun Gupta
This patch introduces an rte pmd API to configure dpdmux from
the application.
dpdmux can work in association with dpni as an additional
distribution capability on the NIC.
Signed-off-by: Nipun Gupta
---
drivers/net/dpaa2/Makefile | 1 +
drivers/net/dpaa2/d
From: Nipun Gupta
The DPAA2 hw can support a special offset based
configuration to program distribution on hash.
This is for all cases, which are not directly supported.
e.g. HASH based distribution on inner ip header
of a GRE tunnel.
Signed-off-by: Nipun Gupta
---
drivers/net/dpaa2/base/dpaa
From: Shreyansh Jain
Initial design was to have the buffer pool per process where a
global static array stores the bpids. But, in case of secondary
processes, this would not allow the I/O threads to translate the
bpid in Rx'd packets.
This patch moves the array to a global area (rte_malloc) and
On Thu, 2018-12-27 at 12:13 +0800, Gavin Hu wrote:
> When CONFIG_RTE_FORCE_INTRINSICS is enabled for x86, the clang
> compilation error was:
> include/generic/rte_atomic.h:215:9: error:
> implicit declaration of function '__atomic_exchange_2'
> is invalid in C99
>
On Thu, 2018-12-27 at 12:13 +0800, Gavin Hu wrote:
> ---
> ---
> From: Joyce Kong
>
> The old implementation is unfair, some threads may take locks
> aggressively
I think, one issue here is x86 and ppc follows traditional spinlock a
On Thu, 2018-12-27 at 12:13 +0800, Gavin Hu wrote:
> ---
> ---
> The test is to benchmark the performance of spinlock by counting the
> number of spinlock acquire and release operations within the
> specified
> time.
> A typical pair o
On Thu, 2018-12-27 at 12:13 +0800, Gavin Hu wrote:
> ---
> ---
> To precisely benchmark the spinlock performance, uses the precise
> version of getting timestamps, which enforces the timestamps are
> obtained at the expected places.
>
On Thu, 2018-12-27 at 12:13 +0800, Gavin Hu wrote:
---
> ---
> The __sync builtin based implementation generates full memory
> barriers
> ('dmb ish') on Arm platforms. Using C11 atomic builtins to generate
> one way
> barriers.
>
> He
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