Friday, August 25, 2017 1:32 PM, Jerin Jacob:
> >
> > The new API does not have an equivalent for the below Tx flags:
> >
> > * ETH_TXQ_FLAGS_NOREFCOUNT
> > * ETH_TXQ_FLAGS_NOMULTMEMP
>
> IMO, it make sense to keep those flags as PMD optimization if an application
> does not need reference count a
The reason for the requirement of a barrier between the txq writes
and the doorbell record writes is to avoid a case where the device
reads the doorbell record's new value before the txq writes are flushed
to memory.
The current use of rte_wmb is not necessary, and can be replaced by
rte_io_wmb wh
from s...@grimberg.me:
When measuring latency when running a latency critical workload on mlx5 pmd
drivers we noticed high latency can occur due to delayed doorbell record update
flush.
This can be reproduced using the simple program [1] against testpmd macswap fwd
mode. This utility sends a r
By default, Verbs maps the doorbell register to write combining.
Working with write combining is useful for drivers which use blue flame
for the doorbell write.
Since mlx5 PMD uses only doorbells and write combining mapping requires
an extra memory barrier to flush the doorbell after its write, se
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