Re: [dpdk-dev] [PATCH v2] mempool/octeontx2: optimize for L1D cache architecture

01/02/2020 12:51, Jerin Jacob: > On Fri, Jan 31, 2020 at 10:53 PM wrote: > > > > From: Pavan Nikhilesh > > > > OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate > > the set selection. > > Add additional padding to ensure that the element size always > > occupies odd number of cacheli

Re: [dpdk-dev] [PATCH v2] mempool/octeontx2: optimize for L1D cache architecture

On Fri, Jan 31, 2020 at 10:53 PM wrote: > > From: Pavan Nikhilesh > > OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate > the set selection. > Add additional padding to ensure that the element size always > occupies odd number of cachelines to ensure even distribution > of elements a

[dpdk-dev] [PATCH v2] mempool/octeontx2: optimize for L1D cache architecture

From: Pavan Nikhilesh OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate the set selection. Add additional padding to ensure that the element size always occupies odd number of cachelines to ensure even distribution of elements among L1D cache sets. Signed-off-by: Pavan Nikhilesh Si