01/02/2020 12:51, Jerin Jacob: > On Fri, Jan 31, 2020 at 10:53 PM <pbhagavat...@marvell.com> wrote: > > > > From: Pavan Nikhilesh <pbhagavat...@marvell.com> > > > > OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate > > the set selection. > > Add additional padding to ensure that the element size always > > occupies odd number of cachelines to ensure even distribution > > of elements among L1D cache sets. > > > > Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com> > > Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com> > > Signed-off-by: Vamsi Attunuru <vattun...@marvell.com> > > Signed-off-by: Jerin Jacob <jer...@marvell.com> > > --- > > v2 Changes: > > ---------- > > - Fix 32bit build break. > > Acked-by: Jerin Jacob <jer...@marvell.com> > > Delegated the patch to Thomas as it has come through the main tree.
Applied, thanks
