Patch enables 3DES-CBC secure capability of crypto device.
Signed-off-by: Vamsi Attunuru
---
drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +-
.../crypto/cnxk/cnxk_cryptodev_capabilities.c | 24 +++
drivers/crypto/cnxk/cnxk_ipsec.h | 3 ++-
3 files changed, 27
Patch enables 3DES-CBC capability of inline crypto device.
Signed-off-by: Vamsi Attunuru
---
drivers/common/cnxk/cnxk_security.c | 3 +++
drivers/net/cnxk/cn10k_ethdev_sec.c | 20
2 files changed, 23 insertions(+)
diff --git a/drivers/common/cnxk/cnxk_security.c
b/drivers
Hi All,
I sent 8 patches, twice today, but these patches are not visible in archive
https://mails.dpdk.org/archives/dev/2022-April/thread.html.
How do I figure out what went wrong with those emails?
Thanks,
Pankaj
Add separate worker thread when all SA's are of type
inline protocol offload and librte_ipsec is enabled
in order to make it more optimal for that case.
Current default worker supports all kinds of SA leading
to doing lot of per-packet checks and branching based on
SA type which can be of 5 types o
Update ethernet header during route lookup instead of doing
way later while performing Tx burst. Advantages to doing
is at route lookup is that no additional IP version checks
based on packet data are needed and packet data is already
in cache as route lookup is already consuming that data.
This i
Store security context pointer in lcore Rx queue config and
get it from there in fast path for better performance.
Currently rte_eth_dev_get_sec_ctx() which is meant to be control
path API is called per packet basis. For every call to that
API, ethdev port status is checked.
Signed-off-by: Nithin
Allow larger burst size of vector event mode instead of restricting
to 32. Also restructure traffic type struct to have num pkts first
so that it is always in first cacheline. Also cache align
traffic type struct. Since MAX_PKT_BURST is not used by
vector event mode worker, define another macro for
Use HW parsed packet type when ethdev supports necessary protocols.
If packet type is not supported, then register ethdev callbacks
for parse packet in SW. This is better for performance as it
effects fast path.
Signed-off-by: Nithin Dabilpuram
Acked-by: Akhil Goyal
---
examples/ipsec-secgw/ips
Enable Tx IPv4 checksum offload only when Tx inline crypto, lookaside
crypto/protocol or cpu crypto is needed.
For Tx Inline protocol offload, checksum computation
is implicitly taken care by HW.
Signed-off-by: Nithin Dabilpuram
Acked-by: Akhil Goyal
---
examples/ipsec-secgw/ipsec-secgw.c | 3
Move fast path helper functions to header file for easy access.
Signed-off-by: Nithin Dabilpuram
Acked-by: Akhil Goyal
---
v4:
- Fix NULL pointer access in patch 7/7's inline protocol single sa worker
thread function when outbound SA doesn't exist.
v3:
- In patch 7/7, in Inline Protocol single
Honnappa Nagarahalli writes:
>
>
>>
>> On Tue, Apr 26, 2022 at 5:05 PM Aaron Conole
>> wrote:
>> > >
>> > > TBH, I did not test Travis by lack of interest (plus I don't want to
>> > > be bothered with their ui / credit stuff).
>> > > We could consider dropping Travis in the near future.
>> > >
Add support for using hugepages for worker lcore stack memory. The
intent is to improve performance by reducing stack memory related TLB
misses and also by using memory local to the NUMA node of each lcore.
EAL option '--huge-worker-stack [stack-size-kbytes]' is added to allow
the feature to be e
On Fri, 29 Apr 2022 14:52:03 -0400
Don Wallwork wrote:
>
> The expectation is that use of this optional feature would be limited to
> cases where the performance gains justify the implications of these
> tradeoffs. For example, a specific data plane application may be okay
On 4/27/2022 4:17 AM, Morten Brørup wrote:
+CC: EAL and Memory maintainers.
From: Don Wallwork [mailto:d...@xsightlabs.com]
Sent: Tuesday, 26 April 2022 23.26
On 4/26/2022 5:21 PM, Stephen Hemminger wrote:
On Tue, 26 Apr 2022 17:01:18 -0400
Don Wallwork wrote:
On 4/26/2022 10:58 AM, Stephe
Reviewed-by: Jochen Behrens jbehr...@vmware.com
From: Pankaj Gupta
Date: Friday, April 29, 2022 at 11:20 AM
To: Jochen Behrens , Yong Wang
Cc: dev@dpdk.org , Pankaj Gupta
Subject: [PATCH 0/8] vmxnet3: V5 and V6
Pankaj Gupta (8):
vmxnet3: Added V5 support
vmxnet3: implement reta query and r
gpu: added second RTX 6000 device ID variant
Added second GPU PCI device ID for RTX 6000
Signed-off-by: Cliff Burdick mailto:cburd...@nvidia.com>>
---
drivers/gpu/cuda/cuda.c| 6 +-
drivers/gpu/cuda/devices.h | 3 ++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/g
build: added NVIDIA ARM implementer ID
NVIDIA ARM CPUs (Xavier, Grace) use implementer ID 0x4e. This patch adds initial
support for the Xavier chip rather than compiling using the generic platform.
Signed-off-by: Cliff Burdick
---
config/arm/meson.build | 18 ++
1 file changed,
Hi everyone,
I'm going to be leaving the UNH IOL, so I've submitted the work that
will be continued by other members of the lab.
Thanks,
Brandon
On Fri, Apr 29, 2022 at 12:16 PM Brandon Lo wrote:
>
> Adds a very basic introduction to JSON vector sets in
> the fips validation example application
Merge crc32 hash calculation public API implementation for x86 and Arm.
Select the best available CRC32 algorithm when unsupported algorithm
on a given CPU architecture is requested by an application.
Previously, if an application directly includes `rte_crc_arm64.h`
without including `rte_hash_crc
Split x86 and SW hash crc intrinsics into a separate files.
Signed-off-by: Pavan Nikhilesh
Reviewed-by: Ruifeng Wang
---
v8 Changes:
- Install arch specific headers as indirect headers.
- Retain `rte` prefix for arch specific headers.
v7 Changes:
- Fix build with ppc and other arch.
v6 Cha
Added function to parse algorithm for CMAC test.
Signed-off-by: Brandon Lo
---
examples/fips_validation/fips_validation.c | 31 +++---
examples/fips_validation/main.c| 3 +++
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/examples/fips_validation/fip
Implemented JSON support for the CMAC test.
Signed-off-by: Brandon Lo
---
examples/fips_validation/fips_validation.h| 6 ++
.../fips_validation/fips_validation_cmac.c| 68 +++
2 files changed, 74 insertions(+)
diff --git a/examples/fips_validation/fips_validation.h
b/e
Adds JSON support for the HMAC algorithm.
Signed-off-by: Brandon Lo
---
examples/fips_validation/fips_validation.c| 2 +
examples/fips_validation/fips_validation.h| 6 ++
.../fips_validation/fips_validation_hmac.c| 93 +++
examples/fips_validation/main.c
Adds json-specific testing and writeback function. Allows
the user to test AES-GCM vector sets.
Signed-off-by: Brandon Lo
---
v3:
* fix checkpatch warnings
examples/fips_validation/fips_validation.h| 3 +
.../fips_validation/fips_validation_gcm.c | 151 +-
examples/fip
Added the ability to use the json format as the input
and output of the example application.
Signed-off-by: Brandon Lo
---
v3:
* fix checkpatch warnings
v2:
* remove use_json variable
examples/fips_validation/main.c | 200 +++-
1 file changed, 196 insertions(+), 4 d
Added functions to parse the required information from a vector set
given in the new json format.
Signed-off-by: Brandon Lo
---
v3:
* fix checkpatch warnings
v2:
* fix for loop initialization
examples/fips_validation/fips_validation.c | 92 ++
1 file changed, 92 insertions(
Added json-specific functions and other information needed to
test the new FIPS test vectors.
Signed-off-by: Brandon Lo
---
v2:
* fix type of prefix to suffix
examples/fips_validation/fips_validation.h | 42 +-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/ex
Added a check for RTE_HAS_JANSSON into the meson
configuration file for JSON support.
Signed-off-by: Brandon Lo
---
examples/fips_validation/meson.build | 4
1 file changed, 4 insertions(+)
diff --git a/examples/fips_validation/meson.build
b/examples/fips_validation/meson.build
index 7eef
Adds a very basic introduction to JSON vector sets in
the fips validation example application. This patch set
will only introduce the AES-GCM test using a JSON request
file because the other algorithms need more information
than what is given in the new JSON format.
Brandon Lo (8):
examples/fips
> On Wed, Apr 27, 2022 at 5:22 PM Pavan Nikhilesh
> wrote:
> >
> > Split x86 and SW hash crc intrinsics into a separate files.
> >
> > Signed-off-by: Pavan Nikhilesh
>
> You still need to keep those headers public.
> Otherwise, this breaks compilation for external applications relying
> on rte_h
On Fri, Apr 29, 2022 at 4:25 PM David Marchand
wrote:
> eventfd creation and a intr_handle->nb_intr++, but does nothing on
Scratch the part about nb_intr++ :-)
I did not re-read before sending.
--
David Marchand
Hello Ferruh,
On Fri, Apr 29, 2022 at 3:56 PM Ferruh Yigit wrote:
> > @@ -442,12 +428,16 @@ fs_rx_queue_setup(struct rte_eth_dev *dev,
> > rxq->info.nb_desc = nb_rx_desc;
> > rxq->priv = PRIV(dev);
> > rxq->sdev = PRIV(dev)->subs;
> > - ret = rte_intr_efd_enable(intr_handle,
On 3/28/2022 4:16 PM, Gaoxiang Liu wrote:
The following log message may appear after a slave is idle(or nearly
idle)
for a few minutes:"PMD: Failed to allocate LACP packet from pool".
And bond mode 4 negotiation may fail.
Problem:When bond mode 4 has been chosed and delicated queue has
not been
From: Elena Agostini
Enable GPU_REGISTERED flag in gpu/cuda driver in the memory list.
If a GPU memory address CPU mapped is freed before being
unmapped, CUDA driver unmaps it before freeing the memory.
Signed-off-by: Elena Agostini
---
drivers/gpu/cuda/cuda.c | 77
On 3/24/2022 3:09 PM, David Marchand wrote:
A intr_handle is being allocated as a hack to get a (proxy) eventfd from
the Linux interrupt implementation.
But this handle is never freed.
Remove this convoluted hack and create an eventfd in Linux case.
Fixes: d61138d4f0e2 ("drivers: remove direct
From: Elena Agostini
Enable GPU_REGISTERED flag in gpu/cuda driver in the memory list.
If a GPU memory address CPU mapped is freed before being
unmapped, CUDA driver unmaps it before freeing the memory.
Signed-off-by: Elena Agostini
---
drivers/gpu/cuda/cuda.c | 78 +---
On 4/29/2022 7:52 AM, Min Hu (Connor) wrote:
Hi, Ferruh,
在 2022/4/27 2:19, Ferruh Yigit 写道:
On 3/24/2022 3:00 AM, Min Hu (Connor) wrote:
From: Huisong Li
All slaves will be stopped and removed when closing a bonded port.
But the
while loop can not stop if both rte_eth_dev_stop and
rte_eth_
On 4/29/2022 7:45 AM, Min Hu (Connor) wrote:
Hi, Ferruh,
在 2022/4/27 2:19, Ferruh Yigit 写道:
On 3/24/2022 3:00 AM, Min Hu (Connor) wrote:
From: Huisong Li
When stopping a bonded port, all slaves should be deactivated. But only
s/deactivated/stopped/ ?
not agreed. deactivated and stopped ar
On Wed, Apr 27, 2022 at 5:22 PM Pavan Nikhilesh
wrote:
>
> Split x86 and SW hash crc intrinsics into a separate files.
>
> Signed-off-by: Pavan Nikhilesh
You still need to keep those headers public.
Otherwise, this breaks compilation for external applications relying
on rte_hash_crc.h.
Example:
Hi Abhinandan,
> This is failing with asym changes. Please look into this.
Thanks for pointing this out. It is failing as null crypto does not support asym
And asym_session_create would need an op from driver which is NULL for null
crypto
Please check if below change is working for you.
diff -
Hi Abhinandan,
Please see inline.
> > +
> > +void *
> > +rte_cryptodev_session_event_mdata_get(struct rte_crypto_op *op) {
> Null check for op?
Null check can be added, but this a datapath dpdk internal API.
We do not normally add checks in datapath.
If you insist, I can add, but before calling t
> Subject: [PATCH v3 1/7] examples/ipsec-secgw: move fast path helper functions
>
> Move fast path helper functions to header file for easy access.
>
> Signed-off-by: Nithin Dabilpuram
> ---
Series
Acked-by: Akhil Goyal
@konstantin.anan...@intel.com: any more comments on this series?
> v3:
Hi Konstantin,
Any comments on this updated series ?
Thanks
Nithin
On 4/28/22 8:34 PM, Nithin Dabilpuram wrote:
Move fast path helper functions to header file for easy access.
Signed-off-by: Nithin Dabilpuram
---
v3:
- In patch 7/7, in Inline Protocol single sa mode's worker thread, further
> TIMER_MILLISECOND is defined as the number of cpu cycles per millisecond,
> current definition is correct for cores with frequency of 2GHZ, for cores
> with different frequency, it caused different periods between refresh,
> (i.e. the definition is about 14ms on ARM cores).
> The devarg that stat
> > The octeontx2 9xxx SoC family support is added.
> >
> > Signed-off-by: Mahipal Challa
> Acked-by: Ashish Gupta
Applied to dpdk-next-crypto
>
> > Subject: [PATCH 1/2] app/crypto-perf: populate mbuf in latency test
> >
> > For decrypt, ICV mismatch can come as data is dummy and
> > latency will be calculated for error path. Hence populate
> > mbuf with test vector data.
> >
> > Signed-off-by: Archana Muniganti
> Acked-by: Akhil Goyal
> > Subject: RE: [PATCH 2/2] app/crypto-perf: add vector file for AES-GCM
> >
> > > Subject: [PATCH 2/2] app/crypto-perf: add vector file for AES-GCM
> > >
> > > Added test vector file for AES-128-GCM for 64B and 512B length
> > > buffers.
> > >
> > > Signed-off-by: Archana Muniganti
> > From wher
> Change-log:
> Fixed git log issues.
>
> Gagandeep Singh (13):
> crypto/dpaa2_sec: fix fle buffer leak
> crypto/dpaa2_sec: fix buffer pool ID check
> crypto/dpaa_sec: fix length for chain FD in raw sec driver
> crypto/dpaa2_sec: fix length for chain FD in raw sec driver
> crypto/dpaa_se
Hi Akhil,
Please see inline.
Thanks,
Archana
> -Original Message-
> From: Akhil Goyal
> Sent: Friday, April 29, 2022 11:31 AM
> To: Archana Muniganti ; ciara.po...@intel.com;
> declan.dohe...@intel.com
> Cc: Archana Muniganti ; Anoob Joseph
> ; dev@dpdk.org
> Subject: RE: [PATCH 2/2] ap
>
> > From: Kiran Kumar K
> >
> > Extended support for asymmetric crypto perf throughput test.
> > Added support for new modulus lengths.
> > Added new parameter --modex-len.
> > Supported lengths are 60, 128, 255, 448. Default length is 128.
> >
> > Signed-off-by: Kiran Kumar K
> Acked-by: Akhi
On Mon, Apr 25, 2022 at 11:26 AM Huisong Li wrote:
> @@ -773,20 +787,8 @@ port_infos_display(portid_t port_id)
> if (!dev_info.flow_type_rss_offloads)
> printf("No RSS offload flow type is supported.\n");
> else {
> - uint16_t i;
> - char
> -Original Message-
> From: Pavan Nikhilesh
> Sent: Wednesday, April 27, 2022 11:23 PM
> To: Ruifeng Wang ; Yipeng Wang
> ; Sameh Gobriel ;
> Bruce Richardson ; Vladimir Medvedkin
>
> Cc: jer...@marvell.com; dev@dpdk.org; Pavan Nikhilesh
>
> Subject: [PATCH v7 2/2] hash: unify crc32 sel
> -Original Message-
> From: Pavan Nikhilesh
> Sent: Wednesday, April 27, 2022 11:23 PM
> To: Ruifeng Wang ; Yipeng Wang
> ; Sameh Gobriel ;
> Bruce Richardson ; Vladimir Medvedkin
>
> Cc: jer...@marvell.com; dev@dpdk.org; Pavan Nikhilesh
>
> Subject: [PATCH v7 1/2] hash: split x86 and S
> From: Kiran Kumar K
>
> Extended support for asymmetric crypto perf throughput test.
> Added support for new modulus lengths.
> Added new parameter --modex-len.
> Supported lengths are 60, 128, 255, 448. Default length is 128.
>
> Signed-off-by: Kiran Kumar K
Acked-by: Akhil Goyal
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