An example application shows how to use opae ifpga APIs.
You can test each API by running corresponding command.
Signed-off-by: Wei Huang
---
examples/ifpga/Makefile| 45 ++
examples/ifpga/commands.c | 1321
examples/ifpga/commands.h | 16 +
example
Cyborg is part of OpenStack, it needs some OPAE type APIs to manage
PACs (Programmable Acceleration Card) with Intel FPGA. Below major
functions are added to meets Cyborg requirements.
1. opae_init_eal() set up EAL environment.
2. opae_cleanup_eal() clean up EAL environment.
3. opae_enumerate() sea
RSU (Remote System Update) depends on secure manager which may be
different on various implementations, so a new secure manager device
is implemented for adapting such difference.
There are three major functions added:
1. ifpga_rawdev_update_flash() updates flash with specific image file.
2. ifpga_
There are three types of property can be got from FPGA, they are
implemented in below functions:
1. ifpga_rawdev_get_fme_property() get property of FME (FPGA
Management Engine).
2. ifpga_rawdev_get_port_property() get property of FPGA port.
3. ifpga_rawdev_get_bmc_property() get property of BMC
Cyborg is part of OpenStack, it needs some OPAE APIs to manage
devices with Intel FPGA. The first three patches implement extra
APIs to meet Cyborg requirement. The last patch add an example
to show how to use these APIs.
Main changes from v3:
- Enclose macro PCI_EXT_CAP_ID in parentheses
Wei Hua
Tested-by: Xie,WeiX < weix@intel.com>
Regards,
Xie Wei
> -Original Message-
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of
> dapengx...@intel.com
> Sent: Wednesday, December 30, 2020 2:54 PM
> To: Wu, Jingjing ; Xing, Beilei
> Cc: dev@dpdk.org; Yu, DapengX ; sta...@dpdk.org
https://bugs.dpdk.org/show_bug.cgi?id=581
murphy (murphyx.y...@intel.com) changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
CC|
From: YU DAPENG
When the interrupt handle instance allows none packet I/O interrupts,
the max value of vector_id is set to be less than the number of msix
interrupts, but not equal to it. Which may cause same vector_id is sent
to PF with opcode VIRTCHNL_OP_CONFIG_IRQ_MAP to setup the cause of
int
An example application shows how to use opae ifpga APIs.
You can test each API by running corresponding command.
Signed-off-by: Wei Huang
---
examples/ifpga/Makefile| 45 ++
examples/ifpga/commands.c | 1321
examples/ifpga/commands.h | 16 +
example
Cyborg is part of OpenStack, it needs some OPAE type APIs to manage
PACs (Programmable Acceleration Card) with Intel FPGA. Below major
functions are added to meets Cyborg requirements.
1. opae_init_eal() set up EAL environment.
2. opae_cleanup_eal() clean up EAL environment.
3. opae_enumerate() sea
There are three types of property can be got from FPGA, they are
implemented in below functions:
1. ifpga_rawdev_get_fme_property() get property of FME (FPGA
Management Engine).
2. ifpga_rawdev_get_port_property() get property of FPGA port.
3. ifpga_rawdev_get_bmc_property() get property of BMC
RSU (Remote System Update) depends on secure manager which may be
different on various implementations, so a new secure manager device
is implemented for adapting such difference.
There are three major functions added:
1. ifpga_rawdev_update_flash() updates flash with specific image file.
2. ifpga_
Cyborg is part of OpenStack, it needs some OPAE APIs to manage
devices with Intel FPGA. The first three patches implement extra
APIs to meet Cyborg requirement. The last patch add an example
to show how to use these APIs.
Main changes from v2:
- Fix coding style issue
Wei Huang (4):
raw/ifpga:
https://bugs.dpdk.org/show_bug.cgi?id=449
Steve Yang (stevex.y...@intel.com) changed:
What|Removed |Added
CC||stevex.y...@intel.com
From: Alvin Zhang
Since the patch '1848b117' has set the value of key in 'struct
rte_flow_action_rss' to NULL, the PMD cannot get the RSS key now.
This patch sets offset and size of the key pointer as the first
parameter of the token 'key' and copies the start address of the
'HEX' data to the lo
Hi Maxime,
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 22/40] net/virtio: remove last PCI refs in
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 21/40] net/virtio: move vring alignment to generic head
Hi Maxime,
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 20/40] net/virtio: make interrupt handling
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 19/40] net/virtio: move config definitions to generic h
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 18/40] net/virtio: move virtqueue defines in generic he
Hi Maxime,
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 17/40] net/virtio: move features definition
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 16/40] net/virtio: introduce generic virtio header
>
>
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 15/40] net/virtio: move legacy IO to Virtio PCI
>
> Th
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 14/40] net/virtio: pack virtio HW struct
>
> This patc
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 13/40] net/virtio: move PCI-specific fields to PCI devi
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 12/40] net/virtio: remove bus type enum
>
> Bus type a
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 11/40] net/virtio: validate features at bus level
>
>
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 10/40] net/virtio: add callback for device closing
>
>
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 09/40] net/virtio: store PCI type in Virtio device meta
Hi Maxime,
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 08/40] net/virtio: force IOVA as VA mode fo
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 07/40] net/virtio: move MSIX detection to PCI ethdev
>
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 06/40] net/virtio: move PCI specific dev init to PCI et
> -Original Message-
> From: Huang, Wei
> Sent: 2020年12月30日 9:54
> To: dev@dpdk.org; Xu, Rosen ; Zhang, Qi Z
>
> Cc: sta...@dpdk.org; Zhang, Tianfei ; Huang, Wei
>
> Subject: [PATCH v1 1/4] raw/ifpga: add fpga rsu function
>
> RSU (Remote System Update) depends on secure manager whic
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:13 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 04/40] net/virtio: introduce PCI device metadata
>
> T
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:13 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 01/40] bus/vdev: add helper to get vdev from eth dev
>
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:13 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 03/40] net/virtio: refactor virtio-user device
>
> Thi
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:13 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 02/40] net/virtio: Introduce Virtio bus type
>
> This
Hi Maxime,
> -Original Message-
> From: Maxime Coquelin
> Sent: Monday, December 21, 2020 5:14 AM
> To: dev@dpdk.org; Xia, Chenbo ; olivier.m...@6wind.com;
> amore...@redhat.com; david.march...@redhat.com
> Cc: Maxime Coquelin
> Subject: [PATCH 05/40] net/virtio: move PCI device init in
An example application shows how to use opae ifpga APIs.
You can test each API by running corresponding command.
Signed-off-by: Wei Huang
---
examples/ifpga/Makefile| 45 ++
examples/ifpga/commands.c | 1321
examples/ifpga/commands.h | 16 +
example
Cyborg is part of OpenStack, it needs some OPAE type APIs to manage
PACs (Programmable Acceleration Card) with Intel FPGA. Below major
functions are added to meets Cyborg requirements.
1. opae_init_eal() set up EAL environment.
2. opae_cleanup_eal() clean up EAL environment.
3. opae_enumerate() sea
There are three types of property can be got from FPGA, they are
implemented in below functions:
1. ifpga_rawdev_get_fme_property() get property of FME (FPGA
Management Engine).
2. ifpga_rawdev_get_port_property() get property of FPGA port.
3. ifpga_rawdev_get_bmc_property() get property of BMC
RSU (Remote System Update) depends on secure manager which may be
different on various implementations, so a new secure manager device
is implemented for adapting such difference.
There are three major functions added:
1. ifpga_rawdev_update_flash() updates flash with specific image file.
2. ifpga_
Cyborg is part of OpenStack, it needs some OPAE APIs to manage
devices with Intel FPGA. The first three patches implement extra
APIs to meet Cyborg requirement. The last patch add an example
to show how to use these APIs.
Main changes from v1:
- Fix coding style issue
Wei Huang (4):
raw/ifpga:
Hi Jingjing,
> -Original Message-
> From: Wu, Jingjing
> Sent: Wednesday, December 30, 2020 9:05 AM
> To: Xia, Chenbo ; dev@dpdk.org; tho...@monjalon.net;
> david.march...@redhat.com
> Cc: step...@networkplumber.org; Liang, Cunming ; Lu,
> Xiuchun ; Li, Miao
> Subject: RE: [PATCH 5/9] vf
Hi Jingjing,
> -Original Message-
> From: Wu, Jingjing
> Sent: Tuesday, December 29, 2020 2:05 PM
> To: Xia, Chenbo ; dev@dpdk.org; tho...@monjalon.net;
> david.march...@redhat.com
> Cc: step...@networkplumber.org; Liang, Cunming ; Lu,
> Xiuchun ; Li, Miao
> Subject: RE: [PATCH v2 5/8] e
An example application shows how to use opae ifpga APIs.
You can test each API by running corresponding command.
Signed-off-by: Wei Huang
---
examples/ifpga/Makefile| 45 ++
examples/ifpga/commands.c | 1321
examples/ifpga/commands.h | 16 +
example
Cyborg is part of OpenStack, it needs some OPAE type APIs to manage
PACs (Programmable Acceleration Card) with Intel FPGA. Below major
functions are added to meets Cyborg requirments.
1. opae_init_eal() set up EAL environment.
2. opae_cleanup_eal() clean up EAL environment.
3. opae_enumerate() sear
There are three types of property can be got from FPGA, they are
implemented in below functions:
1. ifpga_rawdev_get_fme_property() get property of FME (FPGA
Management Engine).
2. ifpga_rawdev_get_port_property() get property of FPGA port.
3. ifpga_rawdev_get_bmc_property() get property of BMC
RSU (Remote System Update) depends on secure manager which may be
different on various implementations, so a new secure manager device
is implemented for adapting such difference.
There are three major functions added:
1. ifpga_rawdev_update_flash() updates flash with specific image file.
2. ifpga_
Cyborg is part of OpenStack, it needs some OPAE APIs to manage
devices with Intel FPGA. The first three patches implement extra
APIs to meet Cyborg requirement. The last patch add an example
to show how to use these APIs.
Wei Huang (4):
raw/ifpga: add fpga rsu function
raw/ifpga: add fpga prop
> if ((cmd == VFIO_USER_DMA_MAP || cmd == VFIO_USER_DMA_UNMAP
> ||
> + cmd == VFIO_USER_DEVICE_SET_IRQS ||
> cmd == VFIO_USER_DEVICE_RESET)
> && dev->ops->lock_dp) {
> dev->ops->lock_dp(dev_id, 1);
About cmd "VFIO_USER_REGION_WRITE", irq
On Sat, 26 Dec 2020 18:08:48 +0200, Tal Shnaiderman wrote:
> diff --git a/lib/librte_eal/windows/meson.build
> b/lib/librte_eal/windows/meson.build
> index 3b2faf29eb..f4c3e2f12c 100644
> --- a/lib/librte_eal/windows/meson.build
> +++ b/lib/librte_eal/windows/meson.build
> @@ -21,4 +21,10 @@ sourc
Hi Stephen,
Should I reference the commit that created rte_mbuf_dyn.h for the Fixes tag?
PS: this is my first time submitting a patch to DPDK, so forgive me if this
is covered in the contributing doc, but I couldn't find anything that
applied to this situation
On Tue, Dec 29, 2020 at 1:10 PM Step
On Tue, 29 Dec 2020 12:41:44 -0700
Ashish Sadanandan wrote:
> The header was missing the extern "C" directive which causes name
> mangling of functions by C++ compilers, leading to linker errors
> complaining of undefined references to these functions.
>
> Signed-off-by: Ashish Sadanandan
Coul
Checkpatch prefers 'unsigned int' over bare 'unsigned'.
Reword the error messages for brevity and clarity
so they don't have to be split across multiple lines.
Signed-off-by: Stephen Hemminger
---
lib/librte_pdump/rte_pdump.c | 28 ++--
1 file changed, 14 insertions(+), 1
The device string has an existing size in rte_dev.h
use that instead of defining our own.
Signed-off-by: Stephen Hemminger
---
lib/librte_pdump/rte_pdump.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/lib/librte_pdump/rte_pdump.c b/lib/librte_pdump/rte_pdump.
Use rte_pktmbuf_free_bulk instead of loop when freeing
packets.
Signed-off-by: Stephen Hemminger
---
app/pdump/main.c | 8
lib/librte_pdump/rte_pdump.c | 6 +++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/app/pdump/main.c b/app/pdump/main.c
index b34bf3
The header was missing the extern "C" directive which causes name
mangling of functions by C++ compilers, leading to linker errors
complaining of undefined references to these functions.
Signed-off-by: Ashish Sadanandan
---
lib/librte_mbuf/rte_mbuf_dyn.h | 9 +
1 file changed, 9 insertio
Hi Balazs,
This could be a regression for your specific usecase.
The commit itself tried to fix promisc as is.
Adding more people to comment/investigate here.
Devendra, could it be that we don't consider subsequent calls of
promisc_enabled + allmulti_enable ?
On 18/12/2020 2:34 pm, Balazs Neme
Hi
> -Original Message-
> From: Shiri Kuzin
> Sent: Monday, December 28, 2020 9:44 PM
> From: Viacheslav Ovsiienko
>
> This patch add support for generating GTP PDU container
> session option for the raw encap and raw decap sets.
> The generated options is single 32-bit word with
> min
> -Original Message-
> From: Shiri Kuzin
>
> From: Viacheslav Ovsiienko
>
> This patch introduces the GTP header individual flag bit fields
> and the header optional word with N-PDU number, Sequence Number
> and Next Extension Header type.
>
> Signed-off-by: Viacheslav Ovsiienko
>
> -Original Message-
> From: Stephen Hemminger
>
> On Sun, 27 Dec 2020 18:06:16 +0200
> Shiri Kuzin wrote:
>
> > +#ifdef PEDANTIC
> > +#pragma GCC diagnostic ignored "-Wpedantic"
> > +#endif
>
> Please do not introduce pragma's for pedantic in standard headers.
> It just clutters th
Hi Kevin,
Update DPDK 18.11.11 (LTS) test result for Intel part. All passed except the
known issues.
* Intel(R) Testing
# Basic Intel(R) NIC testing
* PF(i40e):Passed
known issue: create rule for set hash key, but rule create failed.
* PF(ixgbe):Passed
* VF(i40e):Passed
* VF(ixgbe):Passe
Due to many instances of creating CQ SQ and RQ on DevX, they move to common.
v1: Initial release
v2: Bug fix (sending wrong umem id to FW).
Michael Baum (17):
net/mlx5: fix ASO SQ creation error flow
common/mlx5: share DevX CQ creation
regex/mlx5: move DevX CQ creation to common
vdpa/mlx5
The RQ object in DevX is used currently only in net driver, but it share
for future.
Add a structure that contains all the resources, and provide creation
and release functions for it.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/common/mlx5/mlx5_common_devx.c | 116 ++
Using common function for Tx SQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.h | 8 +--
drivers/net/mlx5/mlx5_devx.c | 160 ++-
2 files changed, 40 insertions(+), 128 deletions(-)
diff --git a/drivers/net/m
Using common function for DevX SQ creation for rearm and clock queue.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.h | 8 +--
drivers/net/mlx5/mlx5_txpp.c | 147 +++
2 files changed, 36 insertions(+), 119 deletions(-)
The mlx5_devx_dbr_page structure was used to allocate and release the
umem of the doorbells.
Since doorbell and buffer have used same umem, this structure is
useless.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/common/mlx5/mlx5_common.c | 122 --
Using common function for Rx RQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.h | 4 +-
drivers/net/mlx5/mlx5_devx.c | 178 +--
drivers/net/mlx5/mlx5_rxtx.h | 4 -
3 files changed, 37 insertions(+), 149 del
Using common function for ASO SQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/common/mlx5/mlx5_common_devx.h | 1 +
drivers/net/mlx5/mlx5.h| 8 +--
drivers/net/mlx5/mlx5_flow_age.c | 94 ++
3 files changed, 30 in
The SQ object in DevX is created in several places and in several
different drivers.
In all places almost all the details are the same, and in particular the
allocations of the required resources.
Add a structure that contains all the resources, and provide creation
and release functions for it.
The PRM calculates page size in 4K, so need to reduce the log_wq_pg_sz
attribute.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/common/mlx5/mlx5_devx_cmds.c | 53
drivers/net/mlx5/mlx5_devx.c | 13 +
2 files changed, 30 insert
Using common function for Tx CQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.h | 6 +-
drivers/net/mlx5/mlx5_devx.c | 182 +++
2 files changed, 31 insertions(+), 157 deletions(-)
diff --git a/drivers/net/ml
Using common function for CQ creation at rearm queue and clock queue.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.h | 9 +--
drivers/net/mlx5/mlx5_rxtx.c | 2 +-
drivers/net/mlx5/mlx5_txpp.c | 147 +++
3 files chan
Using common function for DevX CQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/regex/mlx5/mlx5_regex.c | 6 ---
drivers/regex/mlx5/mlx5_regex.h | 9 +---
drivers/regex/mlx5/mlx5_regex_control.c | 91 ++--
drivers/regex/
Using common function for Rx CQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.c | 8 ---
drivers/net/mlx5/mlx5.h | 3 +-
drivers/net/mlx5/mlx5_devx.c | 142 +--
drivers/net/mlx5/mlx5_rxtx.h | 4 --
4
Using common function for DevX CQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/vdpa/mlx5/mlx5_vdpa.h | 10 +
drivers/vdpa/mlx5/mlx5_vdpa_event.c | 81 +++--
drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 2 +-
3 files changed, 26 inse
The CQ object in DevX is created in several places and in several
different drivers.
In all places almost all the details are the same, and in particular the
allocations of the required resources.
Add a structure that contains all the resources, and provide creation
and release functions for it.
In ASO SQ creation, the PMD allocates umem buffer for SQ.
When umem buffer allocation is fails, the MR and CQ memory are not freed
what caused a memory leak.
Free it.
Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging")
Cc: sta...@dpdk.org
Signed-off-by: Michael Baum
Acked-by: M
Use common function for ASO CQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.h | 8 +---
drivers/net/mlx5/mlx5_flow_age.c | 81 +---
2 files changed, 19 insertions(+), 70 deletions(-)
diff --git a/drivers/net
Using common function for DevX SQ creation.
Signed-off-by: Michael Baum
Acked-by: Matan Azrad
---
drivers/regex/mlx5/mlx5_regex.h | 8 +-
drivers/regex/mlx5/mlx5_regex_control.c | 153 ++-
drivers/regex/mlx5/mlx5_regex_fastpath.c | 14 +--
3 files change
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