On 7 Apr, this message from Peter Cordes echoed through cyberspace:
> Now that I think about it again, maybe the problem is just that the L2
> cache is on the mobo, as well as being shared, so the CPUs have to go
> through the bottleneck bus to get to it.
Yeah, nothing like a backside cache, th
On Sat, Apr 07, 2001 at 03:17:24PM -0700, Taro Fukunaga wrote:
> I don't have the technical background to follow a lot of this thread,
> but I've been studying pthreads, and it seems that whether a certain
> process gets executed more quickly on a multiprocessor computer depends
> on how well the p
I don't have the technical background to follow a lot of this thread,
but I've been studying pthreads, and it seems that whether a certain
process gets executed more quickly on a multiprocessor computer depends
on how well the process uses threads for concurrency. So in a
compilation sc
On Sat, Apr 07, 2001 at 04:26:02AM -0700, Andrew Sharp wrote:
> I'm afraid it's even worse than that. I haven't looked up the
> design specs on the web or anything, but I believe the Daystar
> design is quite poor in a number of ways, some of them not really in
> their control. First, it's not SM
I'm afraid it's even worse than that. I haven't looked up the
design specs on the web or anything, but I believe the Daystar
design is quite poor in a number of ways, some of them not really in
their control. First, it's not SMP, it's really AMP, or Asymetric
MP: only processor 0 gets interrupts.
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