* Tadas Slotkus [110811 00:32]:
>
> > There will be a problem leaving the XIP area cached while trying to
> > write to the flash. At the least this means it's not possible to write
> > the whole flash. Is this intended? What's the plan here?
>
> Should it be possible to map flash contents in c
* Dsouza, Malcolm [110809 14:40]:
> Thanks Corey,
>
>
>
> 1. I agree that before reading through the code, it is better to first check
> if the BIOS guides are available. However I would still like the answer to
> my question if I wish to carry on with the investigation for now.
> 2.
On 8/22/11 1:37 AM, Paul Menzel wrote:
Am Montag, den 22.08.2011, 04:55 +0200 schrieb Alec Ari:
Alec Ari (neotheu...@ymail.com) just uploaded a new patch set to gerrit, which
you can find at http://review.coreboot.org/166
-gerrit
commit d402be72762f60d4b60edf5662d31a14eccb03ec
Author: Alec Ar
* Pedro Armando Ojeda May [110922 07:08]:
> I send you the information requested in the wiki of coreboot.
The chipset is supported, the laptop itself is not.
Please get it working and send a patch! :-)
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On 10/10/11 9:02 AM, Alp Eren Köse wrote:
As written on the subject 'make crossgcc' fails as following:
Skipping GDB as requested by command line
Building IASL 20110623 ... failed
make[1]: *** [build-without-gdb] Error 1
make: *** [crossgcc] Error 2
Anyone knows why?
and the
"util/crossgcc/acpi
* Myles Watson [111012 08:19]:
> On Tue, Oct 11, 2011 at 10:13 PM, Oskar Enoksson wrote:
> > I get the following warnings:
> >
> > APIC: 00 missing read_resources
> > APIC: 01 missing read_resources
> > APIC: 02 missing read_resources
> > APIC: 03 missing read_resources
> > I2C: 01:08 missing rea
* Marc Jones [111014 06:22]:
> On Thu, Oct 13, 2011 at 3:19 AM, She, Kerry wrote:
> > Hello,
> >
> >
> >
> > Some mainboard support more than one family of CPUs with same socket type,
> >
> > Such as SuperMicro/h8scm:
> >
> > http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.
* Marc Jones [111016 10:10]:
> >> > I have created 2 devicetree file :
> >> >
> >> > devicetree_f15.cb for platform with family 15 CPU
> >> >
> >> > devicetree_f10.cb for platform with family 10 CPU
> >> >
> >> >
> >> >
> >> > I changed the makefile to create a symbol link “devicetree.cb” link to
* Alp Eren Köse [111018 11:25]:
> Hi thanks all for your help,
>
> I have arranged the "devicetree.cb" as suggested, you can see it at the
> attachment.
> Put the superio chip under the LPC bridge section, but I didn't get how did
> you
> know it?
>
> Added those to the romstage.c:
> > #include
* Alp Eren Köse [111018 17:02]:
> By the way I do not have a "CMC state machine binary", which it says:
> #We don't ship that, but booting without it is bound to fail
> in the src/southbridge/intel/sch/Makefile.inc file. What is it, how can get
> it?
>
> Is it likely for that to cause this seria
On 10/24/11 3:15 AM, Patrick Georgi wrote:
Therefore, I propose (http://review.coreboot.org/#change,320) to get
rid of the "big bootblock" variant altogether. This might break some
boards (silently: they still build, but they fail on boot), but at
least it forces action to fix them.
Advantage
On 11/22/11 5:20 AM, Kyösti Mälkki wrote:
Hi
Could someone explain the use of boot_cpu() in bootblock_normal.c
main()? I thought only the BSP CPU executes this code (currently)?
I am about to push a change that does early SMP init for hyper-threading
CPUs to allow cache-as-ram implementation. S
On Tue, 22 Nov 2011 08:01:01 +0200, Kyösti Mälkki wrote:
On Tue, 2011-11-22 at 06:30 +0900, Stefan Reinauer wrote:
On 11/22/11 5:20 AM, Kyösti Mälkki wrote:
> Hi
>
> Could someone explain the use of boot_cpu() in bootblock_normal.c
> main()? I thought only the BSP CPU execut
On 12/31/11 5:00 AM, ali hagigat wrote:
I downloaded the coreboot version 4 for a Ubuntu system. When i want to execute
util/crossgcc/make
It stops complaining that there is an error building GDB!
If i want to make without GDB like by buildgcc, it stops , the error
is that it can not find one h
* Daniel Lindenaar [120111 15:13]:
> I understand what you're saying, yet I've gotten my hands on two
> boards with the aforementioned chipsets and a lot of goodies on
> them, so I thought to give it a go before spending €€€ for an
> already supported board (which would obviously be much easier)
>
* Software Developer [120127 12:41]:
> Hi,
> we're evaluating some bootloaders that we could use for our Intel E6xx with
> EG20 platform (its exactly the Kontron nanoETXexpress-TT).
>
> See here: http://us.kontron.com/products/computeronmodules/com+express/
> com+express+mini/nanoetxexpresstt.htm
* ali hagigat [120214 18:48]:
> I have initialized Intel 82815 SDRAM controller but for a special type
> of RAM without reading SPD registers. I know that DRP register is :
> 0xCC. I added the code to Coreboot.
>
> I tested much and concluded that RAM has a problem in a way as you
> guys told me
* Idwer Vollering [120215 17:33]:
> Or: how to start a multicore (hyperthreading) processor as if it were
> a singlecore (non-hyperthreading) processor.
>
> Would it be necessary to configure APIC/IPI in serialice' mainboard
> specific code?
You probably need something like:
/* Send INI
* Julian Shulika [120329 14:28]:
> Hi , everyone! Can I use gdb debug tool with coreboot v4.0? This information
> is
> oudated
>
>
> coreboot has an easy to use interface to the GNU debugger gdb. To enable it,
> add the following two lines to your mainboard's Options.lb:
>
> uses CONFIG_GDB_ST
On 4/2/12 3:26 PM, Paul Menzel wrote:
Dear Duncan, dear Stefan,
Am Montag, den 02.04.2012, 22:36 +0200 schrieb Stefan Reinauer:
Stefan Reinauer (stefan.reina...@coreboot.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/844
-gerrit
commit
* Patrick Georgi [120406 17:32]:
> Am 06.04.2012 17:27, schrieb Marc Jones:
> > Can you be more descriptive to how it fails? Does it hang on that
> > instruction?
> That change might also break on future CPUs (if they finally manage
> to make the TPM stuff secure, so that's a big if)
How so?
Gue
* Kyösti Mälkki [120404 10:54]:
> 3. Microcode updates
>
> The "tiny" bootblock doesn't seem like the correct place for microcode
> updates.
As mentioned in one of the reviews, this is needed on many modern CPUs
before entering Cache As Ram.
Stefan
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On 4/10/12 11:13 PM, Marc Jones wrote:
Stefan, can you explain the requirement or consider how else to only
do this on a processor that requires it?Marc
I will try to reconstruct how this was needed. I might not have the test
system anymore. If it works without now, we should drop that patch ag
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ss.)
In addition to that, I left some occurences of the name in LANL license
headers.
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2 and v3.
>
> Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
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utility, not the coreboot utility alone.
Not sure whether those two table types should be mixed. Especially in
v2. Opinions?
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his once flashrom can work with individual sectors.
//Peter
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hchips.c and
rather add another string for the vendor name?
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)(0UL-archive.len);
Regards,
Stefan
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e *)lb_new_record(header);
> + console->tag = LB_TAG_CONSOLE;
> + console->size = sizeof(*console);
> + console->type = LB_TAG_CONSOLE_SERIAL8250;
Is there a reason you are hardcoding the type here, despite
passing one in add_console? ;-)
> +}
Otherwise I say
en before.
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I agree with CDH that we need to be careful with what we rename, but
this is the one thing that directly exposes all of coreboot to the user.
And some of the payloads, too. So even before lxbios was a
not-so-fitting name. Let's do it.
Acked-by:
ed me migrate over a dozen trees in different states with
nearly no conflicts. It's really trivial in most cases.
Stefan
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* Patrick Georgi <[EMAIL PROTECTED]> [080126 22:40]:
> Am Samstag, den 26.01.2008, 21:31 +0100 schrieb Stefan Reinauer:
> > Is there a reason you are hardcoding the type here, despite
> > passing one in add_console? ;-)
> doh, thanks..
>
> what about the ty
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* Peter Stuge <[EMAIL PROTECTED]> [080125 02:17]:
> On Thu, Jan 24, 2008 at 01:53:00PM +0100, Stefan Reinauer wrote:
> > This is unrelated to your patch, but I don't like that we list all
> > the IDs as defines in flash.h just to put that define in the same
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> as well.
>
> This fixes verification of all SPI flash chips >512 kByte behind an
> IT8716F flash translation chip.
>
> Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
looks reasonable, but i could not test it.
Acked-by: Stefan Reinauer <[EMAIL PROTE
Carl-Daniel Hailfinger wrote:
On 27.01.2008 03:01, Stefan Reinauer wrote:
* Carl-Daniel Hailfinger <[EMAIL PROTECTED]> [080126 02:28]:
while I agree fully with renaming the project, we need to consider the
point where we stop the renaming, also because some code referencing ou
fan
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* Marc Jones <[EMAIL PROTECTED]> [080121 22:14]:
> Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
> Index: LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c
> ===
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nk we have any of those files
> in v1, correct?
Good question. I didnt change anything.
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n absolute no-go! If this is supposed to go in at any
later time please change it.
Stefan
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that area. No need to involve gcc and its stack
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* Myles Watson <[EMAIL PROTECTED]> [080207 20:54]:
>
> Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
> Index: src/cpu/emulation/qemu-i386/northbridge.c
> =
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ht
ron minnich wrote:
On Feb 7, 2008 12:28 PM, Stefan Reinauer <[EMAIL PROTECTED]> wrote:
Do we ever want to define devices and compile them in that we don't want
to use?
That's what I can't figure out. I can't recall why that test is there.
That cod
know.
Stefan
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* ron minnich <[EMAIL PROTECTED]> [080209 17:21]:
> Carl-Daniel, I agree with your comments, will add them, but I need an
> ack from *somebody* :-)
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ires to B, and f.4 and f.5 wires to D.
> */
> + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB,
> M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
> + }
> +};
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ger <[EMAIL PROTECTED]>
Thanks for spotting this. It was on my todo since a while actually. But
since the lar segment stuff got in I can not build v3 anymore, so I
didn't get around it yet.
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* Stefan Reinauer <[EMAIL PROTECTED]> [080210 14:15]:
> * Carl-Daniel Hailfinger <[EMAIL PROTECTED]> [080210 13:02]:
> > Use the existing init_archive function to find the LAR in memory.
> > This fixes the case where the option table was not found depending
> > on
Peter Stuge wrote:
On Sun, Feb 10, 2008 at 02:27:51PM +0100, Stefan Reinauer wrote:
LAR: Start 0xfff0 len 0x10
LAR: Start 0xfffc len 0x3c000 <--
tart forcing people into
reading ACPI relevant information from the coreboot table, we can as
well just do it without ACPI, and make sure we don't get dictated by
external projects don't you think.
Best wishes,
Stefan
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ird_apic" anymore, which is an improvement, too.
Stefan
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* Carl-Daniel Hailfinger <[EMAIL PROTECTED]> [080211 00:08]:
> Add dump_mem_range to dump a memory range.
>
> Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
bloat, bloat, bloat - bloat the bootblock a little more.
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eally cool stuff.
If we can make sure it works on real hw:
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should not be removed. It's so small, it really doesnt hurt.
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Geschäftsführe
/* 1760 == note A6. */
#endif
}
@@ -103,7 +103,7 @@
*/
void beep_long(void)
{
-#if defined(CONFIG_BEEPS) && (CONFIG_BEEPS == 1)
+#ifdef CONFIG_BEEPS
speaker_tone(1760, 2000); /* 1760 == note A6. */
#endif
}
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Stefan.
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