Hi all-
I'm trying to set gfx_uma_size on my X210. From what I can tell, I need to
either use nvramcui / nvramtool to set this, or add a cmos.default file.
However, I'm not clear on how to do this correctly. If I just invoke
nvramtool, I'm told that this coreboot was built without selecting
"CONFI
to build a coreboot
> 8.3.0 toolchain to avoid the possible errors (so that the toolchain
> gets built without Ada).
>
> On Sat, Jan 7, 2023 at 2:51 AM Rafael Send
> wrote:
> >
> > Hi,
> > I'm trying to "make crossgcc" for coreboot, but it fa
4:32 Uhr schrieb Nico Huber :
> Hi Rafael,
>
> On 07.01.23 22:03, Rafael Send wrote:
> > I didn't downgrade the toolchain intentionally, I'm looking to build a
> fork
> > of coreboot for a specific platform (mjg59's X2100 port) that never got
> >
:
> On 07.01.23 23:53, Rafael Send wrote:
> > If I wanted to try your first suggestion, does the toolchain build
> > transcend directories? In order to not mix up trees & versions so far I
> > have just checked out the latest master and the version in question into
>
re as I've
done before (I think), I receive the previously mentioned error.
Apologies for the inaccuracy.
R
Am Sa., 7. Jan. 2023 um 22:52 Uhr schrieb Rafael Send <
flyingfishfin...@gmail.com>:
> Hi,
> Thanks for the suggestion. It built in master, then I copied it to the
> xgcc
Hi,
The weird part is that if I build from the root directory, it DOES say
uuid-dev is found yet the build still fails. Might that be for the
aforementioned reason* " Many tests will indicate that a library is present
if they find the .so. But the .so is useless if you need static linking."*
?
I'v
heers,
Rafael
Am So., 8. Jan. 2023 um 12:47 Uhr schrieb Rafael Send <
flyingfishfin...@gmail.com>:
> Hi,
> The weird part is that if I build from the root directory, it DOES say
> uuid-dev is found yet the build still fails. Might that be for the
> aforementioned reason* " Man
Hi,
As folks may have gathered from my other question about the GCC build
environment, I've been playing around with the old X2100 port (
https://github.com/mjg59/coreboot/tree/x2100_ng).
I got it to build and added the latest version of MrChromebox's Tianocore,
but there's still one issue that ke
;
> On Thu, Jan 12, 2023 at 11:08 AM Rafael Send
> wrote:
>
>> Hi,
>> As folks may have gathered from my other question about the GCC build
>> environment, I've been playing around with the old X2100 port (
>> https://github.com/mjg59/coreboot/tree/x2100_
Morning,
Just checking in to see if anyone had some advice on where I could look to
try and fix this problem. Note that it also happens for sleep and suspend
modes, not just shutdowns.
Thanks,
Rafael
Am Do., 12. Jan. 2023 um 09:16 Uhr schrieb Rafael Send <
flyingfishfin...@gmail.com>:
> Jan 16, 2023, 11:08 by flyingfishfin...@gmail.com:
>
> > Morning,
> > Just checking in to see if anyone had some advice on where I could look
> to try and fix this problem. Note that it also happens for sleep and
> suspend modes, not just shutdowns.
> >
> > Thanks
out to make it work
again..
R
Am Di., 17. Jan. 2023 um 11:33 Uhr schrieb Rafael Send <
flyingfishfin...@gmail.com>:
> Hi,
> The *CMOS *(BIOS) battery is installed, yes. The main power battery is
> not - I can try that later but obviously I should be able to power on the
> thing
Hi,
Total beginner here. In fact, I'm just researching interesting
possibilities for using this and how coreboot works.
In particular, I'm wondering how to create custom payloads, and what sorts
of things can be payloads.
According to the wiki, the target file for a payload is an ELF file.
Howeve
Hi,
If I theoretically had a flash chip that was larger than 128Mb, it requires
3-4 byte addressing.
Does / could coreboot support such large memory, or would the limitation
live somewhere else in the system?
Cheers,
R
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d...
Thanks,
R
On Thu, Mar 28, 2019, 3:08 AM Julien Viard de Galbert
wrote:
> On Thu, Mar 28, 2019 at 06:55:50AM +0800, Rafael Send wrote:
> > Hi,
> > If I theoretically had a flash chip that was larger than 128Mb, it
> requires
> > 3-4 byte addressing.
> >
> &
m factor. If
we can address it, that opens up interesting possibilities for embedding
full OS distributions there (such as my previous question about TinyCore).
Gruß,
R
On Fri, Mar 29, 2019 at 10:10 AM Nico Huber wrote:
>
> Hello Rafael,
>
> On 28.03.19 17:12, Rafael Send wrote:
>
t part I can get in the correct
footprint. It's actually "only" 256Mb / 32MiB.
R
On Fri, Mar 29, 2019 at 12:03 PM Nico Huber wrote:
> On 29.03.19 19:08, Rafael Send wrote:
> > Hi Nico-
> > Can you clarify what you mean by coreboot on x86 is special?
>
> o
Hi,
I was attempting to build TinyCore Linux as a payload for Coreboot.
My previous question concerned packing it up as a bootable floppy for
SeaBIOS (work in progress), but when I was learning about Coreboot I
discovered that the menuconfig has two separate options for booting Linux
directly
I t
Hi,
I'm trying to understand what the "Size of CBFS filesystem in ROM" setting
actually does.
If I make the size of the ROM chip large enough to contain my kernel &
initrd (~15MB in this case) how do I need to modify this parameter?
I've read up on the CBFS documentation, and while that provides
>
> this is only true if the flash chip isn't shared with other firmware
> components. But it often is. If you are running a modern Intel-based
> system, for instance, CBFS size should be at most the size of the
> BIOS partition of the flash.
If I'm building this for qemu for testing, should I ma
Good question, I'd be interested in the answer to this as well if anyone
has some insight.
Cheers,
R
On Fri, Apr 12, 2019 at 7:45 AM Matt B wrote:
> Greetings,
>
> From what I can find, Linux can only chainload another linux kernel. (via
> kexec) Does this mean that a Linux payload like LinuxBo
Hi,
I'm trying to figure out how to build coreboot such that I can boot both
legacy and UEFI systems.
>From what I can tell, most payloads will load either one or the other, but
not both (unless Grub2 can do this - unclear to me).
On the other hand, is it possible to use tianocore + SeaBIOS as th
Hi,
I'm running a Tianocore payload on coreboot and I'm not able to boot
Windows (or Windows installers). I eventually get errors like
"UNMOUNTABLE_BOOT_VOLUME" and "DRIVER_PNP_WATCHDOG".
Some searching leads me to the conclusion that in some cases putting one's
SATA controller in IDE mode allows
Hi,
I'm on the port that Matthew Garrett did for the custom Thinkpad X210,
which has an i7-8650 on it.
I'll check in with him (tbh he's probably on this list anyway).
Thanks,
Rafael
On Thu, Aug 22, 2019, 23:19 awokd via coreboot
wrote:
> Rafael Send:
> > Hi,
>
Hi,
Some of you might have picked up on my somewhat disjointed line of
questions from the IRC, I'm putting this into an email so it's searchable
better.
Quick background, I'm trying to find a way to boot both UEFI and Legacy
disks; turns out it's not so straightforward for someone who doesn't code
Hi,
I'm trying to make some adjustments to my descriptor.
The -D switch results in an error which goes something like "Density
modifications to IFD 2.0 not supported yet".
Is there a version of the tool (or a different tool) which will let me make
these changes?
Note that I seem to be able to re
FWIW I'm currently running a Grub2 payload, which starts either Tianocore
or SeaBIOS from CBFS.
Not a CSM and I think my coreboot has ACPI issues so I haven't actually
been able to boot Windows via SeaBIOS, but it does start and run Linuxes
just fine.
R
On Sat, Nov 2, 2019, 00:54 Matt DeVillier
Hi,
I know a couple folks here are active on Thinkpads.com / familiar with the
X210 port by Matthew.
The stock BIOS doesn't appear to support non-NVME devices in the M.2 slot;
I'm attempting to get a Sunix UPD2018 card working to add USB-C.
With stock BIOS, the card works just fine in the WiFi sl
of logs that would help here out of coreboot?
I'll be building with Tianocore.
Cheers,
Rafael
On Sat, Dec 7, 2019, 04:58 Nico Huber wrote:
> Hi Rafael,
>
> On 07.12.19 07:40, Rafael Send wrote:
> > However, so far nothing I've done lets me detect the Sunix card if I try
ck it's keying. If the keying of the slot is such that it
> can't even accept an nvme drive, then there's your answer right there.
>
> Sincerely,
> -Matt
>
> On Sun, Dec 8, 2019 at 6:12 PM Rafael Send
> wrote:
>
>> Hey,
>> I used the mini PC
ot; once Ubuntu is booted.
I don't have any other PCI cards that I could test here, unfortunately.
How shall I go about debugging this further? Can I get logs out of
coreboot somehow?
Cheers,
Rafael
On Sun, Dec 8, 2019 at 7:53 PM Rafael Send
wrote:
> Hi,
> It's an M-key slot an
Hi,
For the past month or two (I'm not actually sure WHEN it stopped working) I
haven't been able to successfully boot (any) Windows installations using
libgfxinit.
Mid-October I had created some builds that worked, but I'm not sure they
were using master or something else at that point (only kept
m unclear if
THAT's what caused Windows to not work correctly (i.e whether the patch
worked better or not). I guess if I start with the commit I originally used
I can play around with cherry-picking that commit vs the previous patch).
R
On Sat, Dec 28, 2019 at 5:00 AM Nico Huber wrote:
> H
,
R
On Sun, Dec 29, 2019 at 6:31 AM Nico Huber wrote:
> On 29.12.19 10:32, Rafael Send wrote:
> > - I'm running linear frame buffer, but not at native resolution. If I do,
> > the boot menu text gets too small since this is a 13" 2k screen.
> > - Payload is Tian
Hmm. I exported my own vbt on Ubuntu with "cp
/sys/kernel/debug/dri/0/i915_vbt vbt.bin", which worked fine in the past,
but I still get the noise.
Windows 10...
R
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Hi there-
I'd like to increase the size of my flash chip from 8MB to 16MB. From
poking at stuff and asking dumb questions in the #coreboot channel, I've
gathered I need to make the following changes, but I'm not 100% sure these
are correct.
If anyone could look this over and point me in the right
>
> I did this exact thing while porting heads to a new motherboard, as the
> 4mb SPI was too small. Heres the steps, and they work.
Ok now I'm a bit confused. Can you elaborate on what some of your steps do?
- When you set chip size to 16MB but use the stock descriptor, you've
basically got a c
FWIW I use Grub to load either SeaBIOS or Tianocore at boot, defaulting to
Tianocore for this exact problem. Hope that's of some help :)
R
On Fri, Mar 20, 2020 at 1:35 PM Dalao via coreboot
wrote:
> > The Tianocore package which ran on top of SeaBIOS, DuetPkg, was remove
> long ago, so that's n
Hi,
I did have some trouble getting this to work correctly. I believe you must
add it to cbfs with "add-payload" and not just as a regular file.
If that doesn't work let us know, I'll take a look at what exactly I did.
Good luck,
R
On Sat, Mar 21, 2020 at 6:08 AM Dalao wrote:
> > FWIW I use Gru
Hi,
Good to know, I actually at one point did the same (extract working
Tianocore from coreboot binary), so maybe that's how it worked.
Did you figure out why it works when you extract it, but not if you just
add the built blob?
Rafael
On Mon, Mar 23, 2020 at 11:44 PM Dalao wrote:
> > I did ha
Hi,
I've been trying to get a PCIe add-in card working in my X210 M.2 slot for
a couple weeks.
There is a hack to get it recognized which involves writing to one of the
Extended Capability registers from an EFI shell, but apparently something
about the way Coreboot initializes PCI (?) makes these
Hi all-
I wrote up an article (or, more like a step-by-step guide) on how to resize
the BIOS chip from 8MB to 16MB.
This is particularly handy for people (like myself) who want more space for
payloads.
This was done on an X210, but theoretically it should work fine on other
platforms as well, as l
b.com/corna/me_cleaner/issues/80 )
>
> Great work, thanks for contributing!
>
>
>
> On Tue, 5 May 2020 at 22:05, Rafael Send
> wrote:
>
>> Hi all-
>> I wrote up an article (or, more like a step-by-step guide) on how to
>> resize the BIOS chip from 8MB to 1
Hi-
Apparently Matthew (mj...@srcf.ucam.org) made some modifications to allow
booting OS X without Clover. I'm not sure if his changes are current or if
they're specific to the X210 which they were made on / for, but I had the
same question and that was the answer I got at the time. Never tried it
Hi,
Do you already have a 64MB BIOS chip? If not, you first need to check if
your CPU supports that size (that's pretty big, I'd be surprised). If it
does, are you planning to swap the chip?
Assuming the answer to the above is "yes", you'll also need to change the
Intel Firmware Descriptor to reco
I'm also interested in this option & raised it sometime last year. As a
user, I don't have the skills necessary to do it, and was informed of the
same conclusion.
However, I DID succeed in building a coreboot which contains both Tianocore
& SeaBIOS separately, then using Grub to choose which paylo
Hi,
Unsure if appending to the 4.13 announcement email was cool, so here's a
separate thread.
I was using coreboot for a while, but then discovered that something about
it was not accessing hidden PCI devices correctly (not enough expertise to
figure out what).
In my particular case, I'm adding a
via stock BIOS? This is really
the only thing keeping me from straight up switching to coreboot so it'd be
dope to get it working...
Cheers,
Rafael
On Fri, Nov 20, 2020 at 10:36 AM Rafael Send
wrote:
> Hi,
> Unsure if appending to the 4.13 announcement email was cool, so here's a
&
sequence
> before its config space becomes "visible."
>
> Cheers,
> - Tim
>
> On Sun, Nov 22, 2020 at 8:02 PM Rafael Send
> wrote:
>
>> Ok, I have a more formulated question now. TLDR, I got the same result as
>> with 4.12, so there's probably
Hi,
Breaking this out from my other email for title clarity purposes, hope
that's ok.
Anyway, I think my issue comes down to coreboot not being able to access
(?) PCI extended registers in the current setup.
I guess this is a general question: CAN coreboot access the extended
capabilities registe
Hi,
Thanks for the information - it's more than I've had before.
Maybe someone else can shed more light on the exact workings, but in the
meantime I'll take a look at MMCONFIG.
Cheers,
Rafael
On Fri, Nov 27, 2020 at 10:45 AM Rudolf Marek wrote:
> Hi,
>
> On 25. 11. 20
Hi,
I'm investigating adding a custom driver for a device on my system. I'm not
a programmer by any means, so please pardon any silly questions...
I'd like to learn more about how to properly add custom drivers, and how
they are called from devicetrees. First, if there is a resource for this,
coul
Hello there-
I'm assuming this is the right way to ask a general question, but please
let me know if it isn't.
I have an "X62" laptop, which is actually an old Thinkpad X61 with a custom
motherboard in it.
This board has an i7-5600u CPU on it, and I was wondering if it was
possible to build a vers
"MEI device not found". I take it that's good news?
Rafael
On Thu, Feb 23, 2017 at 4:51 AM, Iru Cai wrote:
> Hello,
>
> On Thu, Feb 23, 2017 at 3:46 PM, Rafael Send wrote:
>
>> Hello there-
>> I'm assuming this is the right way to ask a general que
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