On 2021-12-15 06:44, AreYouLoco? wrote:
Since https://del.dog paste service is no longer operating...
I am re-sending the dumps to the mailing list as requested by Nico.
I took a look at those inteltool dumps, and they don't seem to be
consistent with what the schematic shows. As Nico mentio
Issue #401 has been updated by Nicholas Chin.
Akura Ryu wrote in #note-8:
> I've met the same problem on my ThinkPad X200.
>
> I enabled EDK2, and also applied SeaBIOS as secondary payload. It cannot boot
> as well: freezes, and screen remains black.
>
> Is there any
Hi Denis,
Just a quick question about your last reply:
On 1/4/23 09:33, Denis 'GNUtoo' Carikli wrote:
On Wed, 4 Jan 2023 04:37:01 +0100 (CET)
Martin Roth wrote:
Hey Denis, My reply got out of control here. Apologies for the
length, feel free to ignore the top and just skip to my replies. :)
Issue #440 has been updated by Nicholas Chin.
J Nky wrote in #note-12:
> Nicholas Chin wrote in #note-11:
> > Could you run `uname -r` and post the result so that I can see what kernel
> > you are running? Could you also check if the file `/proc/config.gz`
> > (contai
Issue #440 has been updated by Nicholas Chin.
J Nky wrote in #note-5:
> > Hmm, so I'm assuming you are using superiotool from the coreboot-utils
> > package?
>
> Yes. Thanks to your instructions and after installation of `libpci-dev` i was
> able to build it.
>
&
Issue #440 has been updated by Nicholas Chin.
Nicholas Chin wrote in #note-14:
> Apparently on Ubuntu the config can be found under
> `/boot/config-5.19.0-21-generic`. Could you check that? That said, when I
> check that file on a live Ubuntu 21.10 ISO with that sa
Hi Ritul,
Yes, CorebootPayload was deprecated and UEFIPayload should be used
going forward. It should be able to boot a UEFI OS with coreboot.
Tianocore was renamed to edk2, as you probably noticed.
Cheers,
Nicholas Chin
On Mon, Feb 6, 2023 at 10:58 AM ritul guru wrote:
>
> Hi,
> I
Issue #455 has been updated by Nicholas Chin.
shen Liu wrote:
> ``` shell
> sudo ./superiotool
> Found Aspeed AST2400 (id=0x00) at 0x4e
> sudo ./superiotool
> superiotool r4.19-306-g12ec7901b7
> No Super I/O found
> ```
> Does superiotool provide debug s
Issue #455 has been updated by Nicholas Chin.
shen Liu wrote in #note-3:
>
> `Starting program: /home/test/coreboot/util/superiotool/superiotool
> Debuginfod has been enabled.
> To make this setting permanent, add 'set debuginfod enabled on' to .gdbinit.
>
Issue #460 has been updated by Nicholas Chin.
akjuxr3 akjuxr3 wrote in #note-1:
> I vote against renaming any x7x board to ivybridge. Ivybridge is the CPU you
> put into the x7x board. Not the board itself.
> If you put a sandybridge CPU into the socket of the h77pro4-m, then
Issue #461 has been updated by Nicholas Chin.
akjuxr3 akjuxr3 wrote:
> Currently in case of the ability to run as less amount of closed source
> software as possible and still have Microcode updates the reduced Intel ME
> with disabled bit in IFD and the lga1155 or the mobile versions
On 3/16/23 05:11, Joursoir wrote:
Hello again,
First of all, I would like to apologize for any inconvenience caused. I
have carefully reviewed the project "Libpayload based memtest payload"
and have come to the conclusion that it's not aligned with my
interests. I would prefer to work on somethi
On 2023-11-26 10:15, Mike Banon wrote:
Dear friends, I just encountered a menuconfig problem on a fresh
coreboot. Steps to reproduce:
1) Testing environment - fully updated Artix Linux (arch w/o systemd):
6.5.11 linux kernel etc.
2) At the freshly cloned coreboot directory (+ submodules
checkout'
On 2023-11-26 21:42, Keith Hui wrote:
Hi all, We have a problem.
After commit 7eab8ef8b720e8744eea3c6c771bccc217fbe5ed (util/kconfig:
Uprev to Linux 6.2's kconfig) [1], make menuconfig is completely
borked. I found out using git bisect.
After the gerrit link is the output I get when I run 'make
Hi Orion,
On 2024-04-09 18:25, Orion Brewer wrote:
Is there a coreboot BIOS flash available for an unknown motherboard in a
customized PC? The motherboard is more than 10 years old. If there is a
coreboot BIOS flash for it, will it add secure boot and TPM 2.0?
It's impossible to say without m
Hi Jérémy,
In the original thread about romstage VGA text mode on the coreboot
mailing list [1], some ideas were brought up about using this
functionality for early debug messages and porting this to older
platforms. I was interested in these possibilities and started exploring
an implementa
Issue #540 has been updated by Nicholas Chin.
The reason there is no coreboot support for (Intel) ThinkPads newer than
Haswell is because of Intel Boot Guard, an optional feature introduced with
Haswell which prevents firmware that isn't signed by the vendor (so, coreboot)
from booting.
Hi Keith,
I can't speak to the devicetree stuff, but I did find something
interesting regarding the PCH PCIe ports:
p8z77-v and sabertooth_z77 have a third PCIe x4 slot serviced by the
PCH, but the 4 lanes are shared with some other x1 slots and devices.
They can configure the PCIe x4 slot to
Hi Keith,
Hi Nicholas,
Thanks for the reply, and the scoop, and pardon my second email to the
list that essentially asked the same question again.
The hidden register would be a boon to my goals. I have an Asus P8Z77-V
LE Plus board on order that I will soon be able to test the idea on,
si
Hi Keith,
Hi Nicholas,
Thanks for the reply, and the scoop, and pardon my second email to the
list that essentially asked the same question again.
The hidden register would be a boon to my goals. I have an Asus P8Z77-
V LE Plus board on order that I will soon be able to test the idea on,
s
On 2025-01-16 00:48, Keith Hui wrote:
The board is here. For some reason both my old Fedora installation and
SystemRescue failed to boot on it so I can't run autoport yet.
However, I did change that PCIe bandwidth setting and took a SPI flash
dump before and after. That PCH soft strap DID chan
On 2025-01-24 08:31, Keith Hui wrote:
Hello all,
Doing some work with (Bill's) Asus P8Z77-V board and running into some
issues and limits.
See it unfold at https://review.coreboot.org/c/coreboot/+/85413
That said, I've run into a few issues and limits trying to bring
feature parity to it. It w
Issue #586 has been updated by Nicholas Chin.
Autoport doesn't generate the contents of those logs directly; it runs other
tools and then parses the output of some of them. Currently it runs `acpidump`,
which dumps the binary contents of all the ACPI tables as hexadecimal to the
aucpidum
Issue #585 has been updated by Nicholas Chin.
Walter Sonius wrote in #note-3:
> Extracted using `dd` both MSDM and SLIC from `/sys/firmware/acpi/tables/` and
> put `select HAVE_ACPI_SLIC` in the
> `srs/mainboard/hp/snb_ivb_desktops/Kconfig` in the common board section.
> Should
Issue #585 has been updated by Nicholas Chin.
Walter Sonius wrote in #note-5:
> Just tried to add the SLIC file to the existing coreboot tianocore image
> build without `select HAVE_ACPI_SLIC` and re-installed W10 Pro but it
> wouldn't activate.
>From some research it seem
On 2025-05-18 08:43, Eneko X wrote:
> Can you add support for Dell Latitude 5420 please, I still haven't dumped
> the laptop bios but i can still do it in the future
That system almost certainly has Intel Bootguard, which prevents firmware not
signed by the vendor, like coreboot, from booting.
So
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