Hi Keith,
Hi Nicholas,
Thanks for the reply, and the scoop, and pardon my second email to the
list that essentially asked the same question again.
The hidden register would be a boon to my goals. I have an Asus P8Z77-V
LE Plus board on order that I will soon be able to test the idea on,
since it is one of those boards with more devices than PCIe lanes. It is
part of my plan to bring coreboot to all the P8x7x boards. Towards that
goal there are a few patches I'm looking to get in such as
CB:82556,82557,85834, and am still looking for volunteers to boot test
my as yet incomplete ports.
Cheers
Keith
Hi Keith,
I can't speak to the devicetree stuff, but I did find something
interesting regarding the PCH PCIe ports:
> p8z77-v and sabertooth_z77 have a third PCIe x4 slot serviced by the
> PCH, but the 4 lanes are shared with some other x1 slots and devices.
> They can configure the PCIe x4 slot to really be x4, or the 4 lanes
> can be configured as 4 x1 ports for various x1 slots or onboard
> devices. This requires changing a soft strap as well as manipulating
> some GPIOs in the SIO chip, and the devicetree changed to match. I
> have the SIO GPIO part figured out, the soft strap I can only come to
> one possible explanation: reflash SPI descriptor with the changed
soft
> strap and force a platform reset. To verify I'll need to get a board
> and actually check the flash chip for changes.
Changing the IFD at runtime seems like an impractical way to achieve
this, especially since the IFD is normally supposed to be read only. I
suspect there's another, undocumented method to change the
configuration. On ICH/PCH datasheets, there is an RCBA register (Root
Port Configuration Register) that indicates the current port
configuration. On the 7 series PCH's, that is at RCBA32(0x400), bits
3:2
for ports 5-8 and bits 1:0 for ports 1:4. However, these bitfields are
documented as read only in the public datasheets. However, in the
public
ICH9 datasheet (and seemingly only the ICH9 datasheet; other datasheets
like ICH7, ICH8, ICH10, etc don't have this detail) the equivalent
register at RCBA32(0x224) lists the bitfields as R/W, with a note
saying
that writing to them is for debug/testing and should be treated as read
only and modifiable only through hard straps (it seems like ICH9 didn't
use IFD soft straps for this). Based on that note, I assume this
mechanism is intended for testing different PCH PCIe configurations
without reflashing the IFD. I haven't tested this yet on any platform
but it does seem plausible that this mechanism exists on chipsets other
than ICH9.
Cheers,
Nicholas
I did some experimentation on my Latitude E6430 (Ivy Bridge/7 Series
Chipset) by attempting to write to RCBA32(0x400) in
sb/intel/bd82x6x/early_rcba.c:southbridge_rcba_config(). Unfortunately,
that register remained unchanged before and after the write. So I guess
either those fields actually are read only, or there's some other thing
that I'm missing. Perhaps there's some sort of lock that prevents those
bits from being modified if they are indeed writable. I'll probably do
some experimentation on my Latitude E6400 (GM45/ICH9) since that chipset
did explicitly document those bits as read write.
Cheers,
Nicholas
_______________________________________________
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org
