2011/8/2 dove - railing :
> If I said I am prepared to pay for it, what are you going to charge for
> doing this project?
Sorry, I have no idea what (amount of money) to charge, nor how much
work it will be.
Others can most likely provide a better/more satisfying answer.
Idwer
--
coreboot maili
2011/8/15 dove - railing :
> Please tell if you interested in doing this project, leaving aside the money
> issues.
Please use "reply to all", thanks in advance.
Idwer
>
> Regards
>
>
> Meeku
>
> On Sun, Aug 14, 2011 at 6:49 PM, Idwer Vollering wrote:
>
2011/10/5 Alp Eren Köse :
> Anyone has an idea?
>
> Another question is I can't find my mainboard vendor "Axiomtek" in Mainboard
> Vendor selection list in menuconfig as expectedly, but all the chips and
> chipset of it seem to be supported as I see them in coreboot website. Is it
> still possible
px-Push_pin2.jpg
>
>> 2. Make sure you can get serial output
>
> I believe I can do it, the board has an RS232 port, so I guess i need a null
> modem cable to connect it to the computer..
>
>> 3. Choose the most similar supported motherboard
>
> I guess it is the iWave
2011/10/10 Alp Eren Köse :
> As written on the subject 'make crossgcc' fails as following:
> Skipping GDB as requested by command line
> Building IASL 20110623 ... failed
> make[1]: *** [build-without-gdb] Error 1
> make: *** [crossgcc] Error 2
>
> Anyone knows why?
> and the "util/crossgcc/acpica-
Comments inline:
2011/10/17 Idwer Vollering
>
>
> 2011/10/17 Alp Eren Köse
>
>> Hi all,
>>
>> I can't get serial output from the board I am trying to put coreboot on,
>> so I am not able to go any further to see whats going on..
>>
>
>&g
2011/10/17 Alp Eren Köse
> Hi all,
>
> I can't get serial output from the board I am trying to put coreboot on, so
> I am not able to go any further to see whats going on..
>
> The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e.
>
It is likely that you need to set the serial po
ou show the output from "superiotool -deV" too? Thanks.
> Sure you can find the output in the attachment.
>
> By the way all I get is \0x00 when I open the board and another \0x00 when
> I close it..
>
> Thanks in advance,
> Alp
>
>
>
>
> 2011/10/17 Idwer
2011/10/18 Alp Eren Köse
> > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e
> > Register dump:
> > idx 02 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f
> > val ff 52 41 ff fe c0 00 00 00 00 fe c0 ff 00 ff
> > def 00 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00
> >
> >
> > CR24 (idx 24, in
2011/12/30 Prakash Punnoor :
> Hi,
>
>
>
> I am trying to build coreboot with SeaBios (for a new mainboard I am trying
> to port). Initially the build system complained about a broken LD, so I
> built make crossgcc -j1 (iasl compile fails in parallel mode, btw)
Oh? Wasn't that fixed..
http://revi
Or: how to start a multicore (hyperthreading) processor as if it were
a singlecore (non-hyperthreading) processor.
Would it be necessary to configure APIC/IPI in serialice' mainboard
specific code?
See these message [1] [2] [3].
This is the output from two processors with hyperthreading disabled
alICE functionality if SerialICE runs from ROM).
> - The pciutils patch is totally untested, but I expect it to work.
>
> A big THANK YOU goes to Idwer Vollering who tested a dozen iterations of
> this code until I had figured out the very surprising and unique
> properties of the
Op 28 maart 2012 14:52 heeft ali hagigat het
volgende geschreven:
> - Forwarded message --
> From: ali hagigat
> Date: Wed, Mar 28, 2012 at 4:58 PM
> Subject: Re: [coreboot] porting Coreboot to a new motherboard
> To: Kyösti Mälkki
>
>
> Dear Kyösti
>
> I just added 10 "nop"
Op 30 maart 2012 18:59 heeft Marc Dunivan het
volgende geschreven:
>
>
> I have and old HP Pavillion with an Asus M2N68-LA Narra 2 mother board.
> Coreboot hasn't been ported to it. Not asking for it either.
>
>
> I just want to know the northbridge and southbridge it has.
Those would be MC
2008/10/28, Andriy Gapon <[EMAIL PROTECTED]>:
>
>
> allow superiotool to compile and work on FreeBSD
> using the same approach as earlier flashrom port
>
> Signed-off-by: Andriy Gapon <[EMAIL PROTECTED]>
>
> ---
>
> This is tested on FreeBSD 7, dump for W83977EF/EG that I sent previously
> was obta
2012/12/18 David Hubbard :
> Hi all,
>
> On Mon, Dec 17, 2012 at 6:40 AM, Bernhard Urban wrote:
>>
>> On Mon, Dec 17, 2012 at 2:33 PM, wrote:
>> > Rudolf Marek writes:
>> >> Maybe it is slowly time to prepare a patch, I think I will need to write a
>> >> porting guide + specific AGESA bits.
>> >
2013/2/26 Francisco Otero Martínez de Al :
> I didn't flash nothing yet.
> Please advise me if it is safe to load coreboot on this motherboard.
Quoting the logfile: Found chipset "NVIDIA MCP61"
MCP61 is not in this list:
http://www.coreboot.org/Supported_Chipsets_and_Devices so the answer
is no.
2013/4/6 Marc Jones :
> Hi Ward,
>
> I think that the H8QGI has fairly good support (the one SMP late init bug
> noted). I didn't look at the details, but similar boards should be a "easy"
> port. The supermicro boards will often have the pads for the debug header
> for when the going gets tough.
2013/4/11 Pradish M P, ERS, HCLTech :
> Dear coreboot folks
>
> i downloaded the latest source code form coreboot.org , when i tried to build
> the cross compiler
> using the command make crossgcc
>
> it gives the following error
>
> root@test-VirtualBox:~/coreboot# make crossgcc
> Warning: no sui
2013/5/6 Wim Vervoorn :
> Hello,
>
>
>
> I am trying to build CoreBoot from Windows using MingGW.
>
>
>
> After downloading the latest version of the complete package to enable this
> it is possible to build this without problem.
>
>
>
> As this package contains an old version of the tree I updated
2013/5/14 Bin X :
> I apologize if it does not make sense at all since this is my first attempt
> to flash a bios with unmatched bios ID.
>
> I was trying to flash bios on a Itona TC2331 to get rid of the limitation
> they put on of any IDE HDD and USB HDD can’t be larger than 64mb.
coreboot can d
2013/6/25 Gerd Hoffmann :
> Hi,
>
> Two little issues with T60:
>
> First, the keyboard doesn't work on cold boots.
http://www.coreboot.org/SeaBIOS#Other_Configuration_items
You have to create the file etc/ps2-keyboard-spinup:
$ ./encodeint.py ps2-keyboard-spinup 2000
$ hexdump ps2-keyboard-sp
2009/5/22 Urja Rannikko
> Hello all,
>
> First thanks to Uwe for nic3com support and to Mats Erik (IIRC) for helping
> with (or atleast pointing out the lack of) 3C905B support - i just tested a
> SST 29EE010 on an 3C905B-TXNM that had been useless for a while - works :)
>
> Anyways, does anyone
2009/6/2 Carl-Daniel Hailfinger
> On 15.05.2009 01:29, Idwer Vollering wrote:
> > Index: nic3com.c
> > ===
> > --- nic3com.c (revision 501)
> > +++ nic3com.c (working copy)
> > @@ -51,
, 0x1002, 0x4391, 0x1458, 0xb000,
> NULL, NULL, "GIGABYTE","GA-MA78G-DS3H",
> it87xx_probe_spi_flash},
> @@ -787,7 +813,6 @@
>{ "Boser", "HS-6637", },
&g
2010/5/14 Keith Hui
> The original patch was unclean as pork (didn't apply cleanly). Please
> use this one instead.
>
> Thanks Joseph.
>
> And edit your board's romstage similar to patch below:
>
> Index: src/mainboard/asus/p2b-ls/romstage.c
> =
2010/5/14 Keith Hui
BTW enable CAR and try again.
Like this (note that it doesn't boot my asus p2b, rev 1.04):
svn diff src/mainboard/asus/p2b/Kconfig
Index: src/mainboard/asus/p2b/Kconfig
===
--- src/mainboard/asus/p2b/Kconfig
2010/5/16 Keith Hui
> A number of cleanups for 440BX raminit code.
>
> Resolves a number of TODOs items within, and clarified a number of other
> TODOs.
> Change register_values[] from long to u8 (byte). For what we are doing
> this is sufficient and makes it only 1/4 the size.
> Remove a hard-co
2010/8/30 Andreas Schultz
> Hi,
>
> Here is a series of patches wich improve i855 support and a new board
> with that chipset.
>
> The board boots successfully with Seabios into Linux!
>
Nice work. Can you show the output from the console (serial output) ?
Off topic: I'm asking this because I o
ice init
APIC_CLUSTER: 0 init
start_eip=0xc000, offset=0x0010, code_size=0x005b
Initializing CPU #0
CPU: vendor Intel device f29
CPU: family 0f, model 02, stepping 09
POST: 0x60
Enabling cache
>
> Andreas
>
Idwer
>
> On Tue, 2010-08-31 at 02:41 +0200, Idwer Vollering
2010/9/18 Uwe Hermann
> See patch.
>
> This fix is brought to you by SerialICE(tm), thanks!
>
Tested on hardware with an identical southbridge (ASUS P2B rev 1.04),
booting doesn't seem to be affected.
Acked-by: Idwer Vollering
>
> Uwe.
> --
> http://hermann-u
2010/10/2 Stefan Reinauer
> On 10/1/10 11:27 PM, Uwe Hermann wrote:
> > See patch.
> >
> > abuilt-tested.
> >
> >
> > Uwe.
> IMHO the patch makes it really hard to actually see what the code does.
> I think Idwer was recently running into a problem where the use of
> post_code would trash %eax w
2010/10/6 Uwe Hermann
> See patch.
>
Here is a fix for building on 32-bit platforms:
Index: src/northbridge/intel/i440bx/raminit.c
===
--- src/northbridge/intel/i440bx/raminit.c (revision 5917)
+++ src/northbridge/intel/i440bx
2010/10/7 Stefan Reinauer
> On 10/6/10 2:27 PM, Idwer Vollering wrote:
>
> 2010/10/6 Uwe Hermann
>
>> See patch.
>>
>
> Here is a fix for building on 32-bit platforms:
>
> Index: sr
ks when using CONFIG_DEBUG_RAM_SETUP=y.
Apart from that:
Signed-off-by: Uwe Hermann
Acking the second patch (v4_remove_c_includes_i82371eb_2.patch):
Acked-by: Idwer Vollering
>
> > else converting the QEMU target to CAR seems like the other option.
>
> That won'
more inclusions of lib/debug.c after r5929.
>
Does your patch survive abuild for each board ?
>
> Signed-off-by: Sylvain Hitier
>
If it does:
Acked-by: Idwer Vollering
>
> Index: mainboard/gigabyte/ga-6bxe/romstage.c
> ==
2010/10/12 Keith Hui
> Guys,
>
Hi Keith,
>
> I could no longer boot my P3B-F with my Tualeron and r5938. Dies with
> "unknown CPU". I believe it will happen with any Slot 1 440BX boards
> that supports model_6bx CPUs.
>
Can you confirm that this changeset caused the regression:
http://tracker.
Update support for FreeBSD.
Signed-off-by: Idwer Vollering
---
FreeBSD support already existed but doesn't compile without errors on my
fbsd 8.1 machine:
$ gmake
gcc -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing
-Werror-implicit-function-declaration -ansi -ped
Add support for FreeBSD.
Signed-off-by: Idwer Vollering
---
I took the liberty to copy MSR code from flashrom's hwaccess.h.
Patch was written using FreeBSD 8.1, earlier versions might or might not
work.
Index: intelt
2010/10/18 Warren Turkal
> On Sunday, October 17, 2010 09:37:27 am Idwer Vollering wrote:
> > Update support for FreeBSD.
> >
> > Signed-off-by: Idwer Vollering
>
Updated patch attached.
Signed-off-by: Idwer Vollering
> A few questions:
> * Would it be b
2010/10/18 Warren Turkal
> On Sunday, October 17, 2010 09:37:31 am Idwer Vollering wrote:
> > Add support for FreeBSD.
> >
> > Signed-off-by: Idwer Vollering
>
Updated patch attached.
Signed-off-by: Idwer Vollering
> In inteltool.h:
> * Can you please briefly e
2010/10/18 Andriy Gapon
> on 17/10/2010 19:37 Idwer Vollering said the following:
> > Update support for FreeBSD.
> >
> > Signed-off-by: Idwer Vollering vid...@gmail.com>>
>
> BTW: http://www.freebsd.org/cgi/cvsweb.cgi/ports/sysutils/superiotool/
>
I know
2010/11/4 Nils
> Remove banner wrapper function and unify print(k).
>
Index: src/northbridge/amd/gx2/raminit.c
> ===
> --- src/northbridge/amd/gx2/raminit.c(revision 6017)
> +++ src/northbridge/amd/gx2/raminit.c(working copy
2010/11/9 Qing Pei Wang
> see the patch
>
> Nack. Please don't change this, or this will happen (demonstrated using
FreeBSD 8.1 + libpci 3.1.7 + gmake-3.81):
$ gmake clean && gmake
rm -f superiotool *.o
gcc -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing
-Werror-implicit-function
Forwarding this to the list, for reference/proof:
-- Forwarded message --
From: Andreas Schultz
Date: 2010/8/31
Subject: Re: [coreboot] [PATCH 0/3] i855 support
To: Idwer Vollering
Hi,
Attached is the serial output and the configuration i used. However,
there seems to be
* 8;;
+// fadt->x_gpe1_blk.bit_offset = 0;
+// fadt->x_gpe1_blk.resv = 0;
+// fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+// fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}
Index: src/southbridge/intel/i82371eb/Makefile.inc
===
2010/4/12 Keith Hui
> >
> > This patch adds preliminary and untested ACPI support to Intel
> 440BX/82371EB
> > (e.g. ASUS P2B and its variants/similar boards).
> > It focuses on an/the ASUS P2B which comes with three ram slots, hence the
> > change to src/northbridge/intel/i440bx/raminit.c.
> >
>
>
> Is the three or four DIMM choice committed ? Because I don't see it in
> Kconfig:
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/src/mainboard/asus/p2b/Kconfig
>
Found it: http://tracker.coreboot.org/trac/coreboot/changeset/5204
It looks like changing Kconfig for the P2B was overloo
=
--- src/southbridge/intel/i82371eb/i82371eb_fadt.c (revision 0)
+++ src/southbridge/intel/i82371eb/i82371eb_fadt.c (revision 0)
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker
+ * Copyright (C
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5.
Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6 on i865.
Signed-off-by: Idwer Vollering
---
Disabling memory access:
$ sudo setpci -s 6.0 0x04.b=0x0
$ sudo ./inteltool -m | head
2010/11/28 Uwe Hermann
> On Sat, Nov 27, 2010 at 12:02:46PM +0100, Tobias Diedrich wrote:
> > Add acpi_is_wakeup_early to i82371eb and P2B.
> > Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
> > Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
> > uses the same acpi wakeup vecto
2010/11/29 Joseph Smith
>
>
> On Sun, 28 Nov 2010 01:19:18 +0100, Idwer Vollering
> wrote:
> > Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
> > registers on ICH5.
> > Add ICH5 and i865 to the supported chips list.
> > Enable the dump
2010/12/21 Keith Hui :
> As promised. Attached is my fix:
Copy/paste:
Index: src/northbridge/intel/i440bx/raminit.c
> ===
> --- src/northbridge/intel/i440bx/raminit.c (revision 6205)
> +++ src/northbridge/intel/i440bx/raminit.c (work
2010/12/26 Stefan Reinauer
> See patch
>
Nice. Can you extend it so the serial port number, "#define DEBUG_PORT
PORT_SERIAL1", in $seabios_dir/src/output.c is shared with
CONFIG_CONSOLE_SERIAL_COM1 in coreboot's .config, and so on for COM2..4 ?
Dito for "#define CONFIG_DEBUG_LEVEL 1" in $seabios
2011/1/8 Roger
> On Fri, Jan 07, 2011 at 10:45:40PM +0200, Jouni Mettälä wrote:
> > Hi
> > Parts of original patch are already in coreboot. This version made
> cache
> > work in my board now. It might need work so it doesn't break others.
> Here
> > is part of serial capture. Rest is atta
2011/2/1 James Wall
> Hello all,
> I have a ECS 848P-A7 that I was wondering if it could be supported since
> all the chipset chips were already listed as being supported.
No, the Intel 848P currently isn't supported but the datasheet can be found
here: http://www.intel.com/design/chipsets/data
2011/2/19 Keith Hui :
> I am trying (again) to get the Adaptec SCSI on my P2B-LS to initialize
> properly with coreboot. But it won't boot.
>
> Attached is a serial log of what happened.
>
> After compiling coreboot I checked out SeaBIOS through git and added
> the SCSI option rom extracted from my
2011/3/2 Keith Hui
> ---
> First, Mysterious breakage on experimental i82371eb ACPI stuff
>
> Rudolf, Idwer, and anyone that tried doing ACPI for the ASUS P2B
> series of boards:
>
> I'm seeing mysterious compiler breakge after updating my local copy to
> r6424. I copied that from P2B to P2B-LS a
2011/3/10 Peter James
> Just wondering if any further progress has been made to the intel 82855
> chipset which as far as I can tell is in a WIP status. Has anyone been able
> to get this working successfully?
>
Apparently not/not really. What board images have you tried to boot:
digitallogic/a
2011/3/29 Georgi, Patrick :
> Am Dienstag, den 29.03.2011, 16:22 +0530 schrieb sharib khan:
>> sharib/coreboot]$ make menuconfig
>> "Makefile", line 23: Missing dependency operator
>> "Makefile", line 25: Need an operator
>> Error expanding embedded variable.
>
>
>> Could anyone tell what am I miss
c-6240
azza/pt-6ibd
biostar/m6tba
compaq/deskpro_en_sff_p600
emulation/qemu-x86
gigabyte/ga-6bxc
gigabyte/ga-6bxe
msi/ms6119
msi/ms6147
msi/ms6156
nokia/ip530
soyo/sy-6ba-plus-iii
tyan/s1846
Signed-off-by: Idwer Vollering
---
Index: src
2011/4/1 Stefan Reinauer :
> * Idwer Vollering [110401 20:29]:
>> Signed-off-by: Idwer Vollering
>>
>> ---
>>
>> Index: src/southbridge/intel/i82371eb/Makefile.inc
>> ===
>> --- src/sout
V2.
Signed-off-by: Idwer Vollering
---
Index: src/southbridge/intel/i82371eb/Makefile.inc
===
--- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474)
+++ src/southbridge/intel/i82371eb/Makefile.inc (working copy)
@@ -24,8
2011/4/5 James Wall :
> Hello all,
> What is the status of the i865 memory controller?
That chipset as a whole is (currently) unsupported, however plans to
support it are there.
RAM init is work in progress, another developer and I have a total of
three i865 boards. Since RAM init is the hardest p
2011/4/6 James Wall :
>
> I will look at the source code then for more ideas and to help understand
> the code then. thanks for the information.
If you want to help porting, can you produce a serialice log (and send
it to Josephd and me, offlist) ? See the website, www.serialice.com
for installati
2011/4/1 Keith Hui :
> ping?
Adds support for initializing registered SDRAM modules on Intel 440BX
> northbridge.
>
> Drops unneeded romcc-inspired programming tricks.
>
> Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC
> module has been detected
> in a row via SPD; also drop
2011/4/18 Peter Stuge :
> Marek wrote:
>> What about the DB_PORT programming header?
http://hardforum.com/showthread.php?t=1598236
>
> Maybe! Can you trace the connections from the port to the flash
> chips?
>
>
>> Is the dual BIOS stored on the MX25L1606EM2I-12G chip?
>
> GIGABYTE boards that ac
2011/4/20 David Bein :
> Hello Idwer,
Hello David,
>
> Thank you very much for the assistance. I assume
> that something like: nvramtool -c 0 will force the
> newly booted bios to re-compute the checksum on the cmos?
I assume you want to save the current contents with "nvramtool -b
cmos_content
2011/4/22 Schenk, John :
>
> Could anyone help in identifying the Phoenix BIOS Chip on the motherboard?
It looks like the chip is just below the lower right corner of the
cardbus frame: http://www.techex.biz/ebaybiz/pics/Motherboards/MBD-00544_02.jpg
>
> The objective is to replace and possibly e
2011/5/16 Scott Duplichan :
> If you happen to want to test windows xp setup
> using a standard setup CD, windows will not find the drives because
> it has no AHCI support. The standard solution is the F6 floppy method
> of adding an AHCI driver, but lack of floppy support on new boards
> makes thi
2011/5/27 Cui Lei :
> I had the same error, just install the lastest binutils, try again.
Quote: "If you have compiler or binutils trouble, REPRODUCE WITH
coreboot/util/crossgcc and then send a log to the mailing list"
>
>
> i try to do a build Of core boot and I get this after running make.
> Th
2011/6/19 dove - railing :
> I have phoned Australia and spoke to an expert in Procon.com.au about 2
> times and corresponded via email. Procon.com.au are wanting several hundred
> dollars whether it's my font or theirs. This is not affordable. I don't
> know why vga bios is proprietary still a
2012/5/23 :
> Hello all,
>
>
>
> I check out coreboot and build and run persimmon project via menuconfig,
Are you using a payload? If so, which one are you using?
>
> Mainborad: AMD
>
> Mainboard Model: Persimon
>
> FlashSize: 4MB
>
>
>
> But it always show 0x00 on my PCI debug card.
Have you c
2012/6/6 Ross McDonald :
> Hello! I would like to use CoreBoot on my laptop. It is an HP Compaq NC6320.
> The board vendor is HP. It is a
> HP 30AA motherboard with an Intel 945GM Chipset (ICH7-M southbridge and i945
> northbridge). The CPU is an Intel Core 2 Duo T5600. It has a SMSC LPC47N217
> Su
2012/6/25 Tomi Leppänen :
> Hi,
>
> I have a Gigabyte GA-6BXE (Rev 2.1) motherboard with coreboot (built last
> week, I think). My processor is Intel Pentium III 550 and I have 786 MiB of
> RAM (actually 1 GiB but the motherboard can't see a part of it). It works
> just fine when I connect graphics
2012/7/6 Michael Büchler :
> On Fri, 2012-07-06 at 13:10 +0200, Michael Büchler wrote:
>> I'm trying to run coreboot on an ASUS A8V-E Deluxe. It stops with a
>> SIGILL after saying the following (tail of the log I got over serial):
>
> I was able to get around this by using gcc-4.4.6 instead of gcc
2012/7/2 Sven Schnelle :
> Carl-Daniel Hailfinger writes:
>
>> [adding coreboot mailing list to CC]
>>
>> Am 29.06.2012 16:49 schrieb Stefan Monnier:
You do know that all Thinkpad T60/X60 can replace the BIOS with coreboot?
>>> No, I didn't, that would be wonderful news.
>>> I see a few menti
2012/7/8 Peter Stuge :
> Idwer Vollering wrote:
>> I have a X60 (1707-CTO / 1707YAU) that won't boot Linux (it
>> segfaults while booting either a 32- or 64-bit kernel/distribution)
>> at all, with ACPI enabled.
>
> What does the failed boot look like? Maybe you co
2012/7/9 ron minnich :
> On Sat, Jul 7, 2012 at 6:24 PM, Idwer Vollering wrote:
>
>> netconsole won't - afaik - work because IP (UDP) isn't
>> functional/loaded at the time of the crash..
>
> hi, did not check this, but you did not used to need IP or any kind u
2012/7/14 Motiejus Jakštys :
> On Fri, Jul 13, 2012 at 10:43 AM, Motiejus Jakštys
> wrote:
>> On Thu, Jul 12, 2012 at 1:26 PM, Tomasz Ostaszewski
>> wrote:
>>> Hi Peter, Motiejus,
>>> Tried to ask on the flashrom mailing list but to no response.
>>> There is a thread about the X60s update fro
2012/7/15 David Griffith :
>
> Would it be worthwhile, at least as an learning experience, to port Coreboot
> to the Thinkpad T42?
My advice is to make i855 work on a desktop machine first.
lspci of a thinkpad t42:
http://www.linuxquestions.org/hcl/showproduct.php/product/3047/cat/all
--
coreboo
2012/7/26 wx :
> How can get 3rd party bins like mrc.bin for SandyBridge/Ivybridge ?
Besides having the possibility to extract mrc.bin with cbfstool, you
can 'download' at least one mrc.bin from the blobs repository:
git clone http://review.coreboot.org/p/blobs.git
> Folder 3rdparty is empty whe
CC: flash...@flashrom.org
2012/9/15 Keith Hui :
> Hi all,
>
> I'm back. With a new laptop.
>
> I'm now rocking a Lenovo x230 tablet, dual-booting Windows 7 and
> Fuduntu, both 64-bit. Knowing the last time I contributed to coreboot
> it was the good old 440BX when life was much simpler, it could b
2012/10/14 coreboot :
> #188: gcc-4.7 miscompiles coreboot on -Os, -O1,-O2,-O3 in 3 different ways
> -+--
> Reporter: mustrumr97@… | Owner: stepan@…
> Type: defect|Status: new
> Priority: major
2012/10/15 Hristo Venev :
> Is it a gcc bug or is it a coreboot bug?
Actually it is a binutils 'bug'. You should run 'make crossgcc' (and
remove .xcompile) in the top directory, where you run 'make
menuconfig'.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listi
2012/10/15 Hristo Venev :
> Binutils bug or feature?
Rather a distribution feature.
http://www.coreboot.org/Development_Guidelines#Required_Toolchain -->
"Linux distributions usually modify their compilers in ways
incompatible with coreboot. If in doubt, use our toolchain."
--
coreboot mailing
Please reply with "reply to all", thanks.
2012/10/15 Hristo Venev :
> Fixed it by using my linux distribution's toolchain but specifying -march=i686
> Probable reason: some instructions enabled by default by gcc but not enabled
> at
> early stages of booting.
Hm, I suppose that i686 is not (exac
2012/11/1 :
> Thank you for this tip.
>
> I followed the instructions (make crossgcc), but got stuck while building gcc
> on a 'bus error' of genautomata.
>
> Details (total of 3):
>
> 1. Output of make crossgcc:
>
> Indus ~ # cd /usr/src/coreboot/
> Indus coreboot # make crossgcc
> Welcome to th
2012/11/1 :
>
> Thx for replying.
>
> I switch to this email address, trying not to pollute the mailing list.
Please keep coreboot@ in the To: or CC field, others can't help you
when you don't use reply-to-all.
>
> I think is not a hardware problem, as the error occurs on the same plae
> everyt
Mimicked from flashrom.c, see patch.
Signed-off-by: Idwer
Index: README
===
--- README (revision 3854)
+++ README (working copy)
@@ -21,7 +21,7 @@
Usage
-
- $ flashrom [-rwvEVfh] [-c chipname] [-s exclude_start] [-e exclude_e
2009/5/13 Uwe Hermann
> On Wed, May 13, 2009 at 12:05:32PM +0200, Carl-Daniel Hailfinger wrote:
> > Acked-by: Carl-Daniel Hailfinger
>
> Thanks, r499.
>
>
> Uwe.
> --
> http://www.hermann-uwe.de | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software
2009/5/13 Uwe Hermann
> On Wed, May 13, 2009 at 12:05:32PM +0200, Carl-Daniel Hailfinger wrote:
> > Acked-by: Carl-Daniel Hailfinger
>
> Thanks, r499.
>
>
> Uwe.
> --
> http://www.hermann-uwe.de | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software
2017-04-23 19:55 GMT+02:00 Michael L. Wilson :
> Hello Idwer Vollering,
>
> I came across an old mailing list item concerning the H8SGL Opteron
> motherboards.
>
> https://mail.coreboot.org/pipermail/coreboot/2013-April/075629.html
>
> Is it truly the case that the single s
2017-04-24 21:08 GMT+02:00 Nagabhushan Shastry :
> Hi,
>
> I am trying to bring up the AMD G series Olive hill plus mainboard with
> coreboot.
>
> These are the options i have enabled in make menuconfig but I am not able
> to see anything on the screen when i power on the board.
> Could someone pl
Do you have access to, or read, the relevant datasheet(s)?
http://www.intel.com/Assets/PDF/datasheet/322896.pdf for example
appiies to NM10 and describes the bits involved on section 13.7.5
(RST_CNT).
2017-04-28 12:46 GMT+02:00 :
> Hi,
>
>
>
> Is there a way to do warm reset in Rangeley based sy
It's installed through the liblzma-dev package:
https://packages.debian.org/stretch/amd64/liblzma-dev/filelist
2017-06-26 15:13 GMT+02:00 Dhanasekar Jaganathan :
> Hi All,
>
> I am trying to enable ethernet in coreboot + GRUB2. So I have enabled
> following option in make meuconfig,
>
> 1. Payload
2017-12-03 12:35 GMT+01:00 ingegneriafore...@alice.it
:
> Hello guys,
>
> I apologize with you for the strange question.
>
> Can you tell me if some of you uses coreboot with the Freebsd Operating
> system on its machine ?
Yes, I'm running -CURRENT on an ASUS F2A85-M board with SeaBIOS as the payl
2013/8/27 matti christensen
> /mc
> matti christensen
> ---keep-IT-simple---
>
No one can, or will, help you when you don't include any information at all.
Which linux distribution are you using?
Did you run 'make crossgcc' ?
coreboot supports three [1] epia-m boards, which one do you have?
[1
2013/10/29 Haywood-Evans Matthew :
> Hi,
>
> I am presently looking at trying to get Coreboot up and running on an
> ASUS F2A85-M system. I am however running into some issues.
>
> Using a bus pirate and flashrom I first backed up the original bios,
> then erased the chip and restored the bios to e
2013/10/29 Idwer Vollering :
> 2013/10/29 Haywood-Evans Matthew :
>> Hi,
>>
>> I am presently looking at trying to get Coreboot up and running on an
>> ASUS F2A85-M system. I am however running into some issues.
>>
>> Using a bus pirate and flashrom I fir
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