Comments inline: 2011/10/17 Idwer Vollering <[email protected]>
> > > 2011/10/17 Alp Eren Köse <[email protected]> > >> Hi all, >> >> I can't get serial output from the board I am trying to put coreboot on, >> so I am not able to go any further to see whats going on.. >> > >> The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e. >> > > It is likely that you need to set the serial port's speed in romstage.c: > > // omitting includes, license header > #include "superio/winbond/w83627hf/early_serial.c" > #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) > > Add this line to main(): > w83627hf_set_clksel_48(SERIAL_DEV); > The bit that controls the clock speed is in CR24. > > >> >> I couldn't figure out where to put the "chip superio/winbond/w83627hf" >> section in the "devicetree.cb" file layout? >> > > SCH boards don't use the serial port but the EHCI debug port to show output > on? See src/mainboard/iwave/iWRainbowG6/devicetree.cb, it doesn't have the > superio included. > > What I would do is put it inside the LPC bridge section, note that I don't > know how the superio is actually attached and therefore could be wrong. > So: > chip southbridge/intel/i82801ex > Replace i82801ex with sch, ofcourse. > device pci 1f.0 on # lpc bridge > chip superio/winbond/w83627hf > end # superio > end # 1f.0 > > > >> Could someone please explain the devicetree.cb file structure? or point a >> way? >> >> The "lspci -tvnn" output and my modified "devicetree.cb" file are at the >> attachment. >> > Can you show the output from "superiotool -deV" too? Thanks. >> Thanks in advance, >> Alp >> >> -- >> coreboot mailing list: [email protected] >> http://www.coreboot.org/mailman/listinfo/coreboot >> > >
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