[coreboot] Fw: Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Samek, Jan
Hello Michał, No need to apologize for discouragement, this is a valuable information I wish I had earlier before I invested so much time into trying to solve the issue (I should've asked earlier ofc.). At least the hope is that the production units should work. Now I guess it's time for us to

[coreboot] Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Samek, Jan
Hello again Michal, I'd like to additionally ask you about a small detail regarding to the issue: What was the stepping that started to work? I'm currently encountering this behavior on B-0. I really did have some really bad memory init errors on A-0 which was considered an engineering sample an

[coreboot] Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Naresh G. Solanki
I remember working on an issue related to "FSP asserts on IOM ready check" I guess on ICL RVP It got fixed for me after making sure proper IOM binary was added using the fit tool. I'm sure your setup is able to boot with vendor provided bios. Then other option is that you can extract iom.bin from

[coreboot] Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Michał Żygowski
Hello Jan, On 24.08.2021 11:08, Samek, Jan wrote: Hello again Michal, I'd like to additionally ask you about a small detail regarding to the issue: What was the stepping that started to work? According to the bug I have issued, the problems gone with B0 stepping: https://bugzilla.tianocore.

[coreboot] Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Michał Żygowski
On 24.08.2021 11:45, Naresh G. Solanki wrote: I remember working on an issue related to  "FSP asserts on IOM ready check" I guess on ICL RVP It got fixed for me after making sure proper IOM binary was added using the fit tool. I'm sure your setup is able to boot with vendor provided bios. The

[coreboot] Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Naresh G. Solanki
If its possible to verify the same by extracting binaries using a fit tool will be the best. Ideally CRC of IOM, MG & TBT fw CRC should match with that of working UEFI bios. Also enabling CR4.MCE may help when things go wrong as it triggers exception handler. If you have itp/dci/csript, then plea

[coreboot] Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Michał Żygowski
Hi Naresh, On 24.08.2021 13:43, Naresh G. Solanki wrote: You mentioned: "engineering sample PCH have been forcing the ME into disabled state" Is this seen with UEFI bios ? Yes it is. I have observed it running the shipped Intel UEFI firmware as well. Regards, Naresh Solanki Best regar

[coreboot] Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Naresh G. Solanki
Please verify based on other points I mentioned. If possible start with fit tools On Tue, Aug 24, 2021 at 5:21 PM Michał Żygowski wrote: > Hi Naresh, > > On 24.08.2021 13:43, Naresh G. Solanki wrote: > > You mentioned: "engineering sample PCH have been forcing the ME into > > disabled state" > >

[coreboot] Re: TigerLake RVP TCSS init failure

2021-08-24 Thread Samek, Jan
Hello Naresh, Thanks for the tip with IOM. I will definitely revisit the blob handling (including IOM) on my side because I think that's not the part I can be proud of in my development setup. The chance of something going wrong here is rather high. When I remove the mca_configure() call, the f

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

2021-08-24 Thread Sumo
Hi Furquan, I can confirm your proposal is working, could you please submit the patch for review? Thanks, Sumo On Fri, Aug 20, 2021 at 9:52 PM Szafranski, MariuszX < mariuszx.szafran...@intel.com> wrote: > Hi Furquan, > > Thanks for pointing. I`ve missed this patch series. > Yeah omitting the `