Hello Jan, On 24.08.2021 11:08, Samek, Jan wrote:
Hello again Michal, I'd like to additionally ask you about a small detail regarding to the issue: What was the stepping that started to work?
According to the bug I have issued, the problems gone with B0 stepping: https://bugzilla.tianocore.org/show_bug.cgi?id=3219 I have been advised to use Bx stepping (so any other tha Ax which is engineering sample). SOme more detaisl on FSP GitHub as well
https://github.com/intel/FSP/issues/63
I'm currently encountering this behavior on B-0. I really did have some really bad memory init errors on A-0 which was considered an engineering sample and swapping for B-0 solved it. Nevertheless, this MCE issue still persists on B-0 in my case. Thanks for info. Regards, Jan Samek Siemens, s.r.o. ADV D EU CZ AE AC 7 jan.sa...@siemens.com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
Best regards -- Michał Żygowski Firmware Engineer GPG: 6B5BA214D21FCEB2 https://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
