https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/92338
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KanRobert wrote:
Merge the two tests into one and put it under apx directory.
https://github.com/llvm/llvm-project/pull/92338
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@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
--
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -346,6 +346,9 @@ def FeatureNF : SubtargetFeature<"nf", "HasNF", "true",
"Support status flags update suppression">;
def FeatureCF : SubtargetFeature<"cf", "HasCF", "true",
"Support conditional faulting">;
+de
https://github.com/KanRobert deleted
https://github.com/llvm/llvm-project/pull/92338
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@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+switch (Constraint[1]) {
+default:
+ break;
+case 'R':
+ if
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
@@ -131,7 +131,7 @@ class X86OpcodePrefixHelper {
// | RM (VR) | EVEX_X | EVEX_B | modrm.r/m | VR | Dest or Src |
// | RM (GPR) | EVEX_B' | EVEX_B | modrm.r/m | GPR | Dest or Src |
// | BASE | EVEX_B' | EVEX_B | modrm.r/m | GPR | MA |
- //
@@ -926,7 +951,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o,
unsigned &i) const {
else
o << "IC_VEX";
- if ((index & ATTR_EVEX) && (index & ATTR_EVEXL2))
+ if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU))
+; // Ignore ATTR_VEX
@@ -575,6 +575,31 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_EVEX_W_NF:
case IC_EVEX_W_B_NF:
return false;
+ case IC_EVEX_B_U:
+ case IC_EVEX_XS_B_U:
+ case IC_EVEX_XD_B_U:
+ case IC_EVEX_OPSIZE_B_U:
+ case IC_EVEX_W_B_U:
+ case IC_EVEX_W
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
@@ -1219,6 +1219,9 @@ static int getInstructionID(struct InternalInstruction
*insn,
attrMask |= ATTR_EVEXKZ;
if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXB;
+ if (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) &&
+
@@ -575,6 +575,31 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_EVEX_W_NF:
case IC_EVEX_W_B_NF:
return false;
+ case IC_EVEX_B_U:
+ case IC_EVEX_XS_B_U:
+ case IC_EVEX_XD_B_U:
+ case IC_EVEX_OPSIZE_B_U:
+ case IC_EVEX_W_B_U:
+ case IC_EVEX_W
@@ -1219,6 +1219,9 @@ static int getInstructionID(struct InternalInstruction
*insn,
attrMask |= ATTR_EVEXKZ;
if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXB;
+ if (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) &&
--
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/101452
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@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
@@ -214,6 +214,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_W_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX_W);
+else {
+ errs() << "Instruction does not
KanRobert wrote:
Is this fail related to your PR?
```
LLVM-Unit :: tools/llvm-cfi-verify/./CFIVerifyTests/2/49
```
https://github.com/llvm/llvm-project/pull/101616
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@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
@@ -785,9 +785,9 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
raw_ostream &o2,
break;
}
- // We assume that the index can fit into uint16_t.
- assert(sEntryNumber < 65536U &&
- "Index into ModRMDecision is too large for uint16_t!");
+ // We
https://github.com/KanRobert approved this pull request.
https://github.com/llvm/llvm-project/pull/101825
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https://github.com/KanRobert commented:
LGTM
https://github.com/llvm/llvm-project/pull/101598
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/101783
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https://github.com/KanRobert commented:
LGTM for the fold table change
https://github.com/llvm/llvm-project/pull/101599
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https://github.com/KanRobert approved this pull request.
MC and foldtable change LGTM
https://github.com/llvm/llvm-project/pull/101600
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/104781
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Author: Shengchen Kan
Date: 2024-06-24T15:11:07+08:00
New Revision: 45a7af7c993f66044a8492dce1d073380feafffc
URL:
https://github.com/llvm/llvm-project/commit/45a7af7c993f66044a8492dce1d073380feafffc
DIFF:
https://github.com/llvm/llvm-project/commit/45a7af7c993f66044a8492dce1d073380feafffc.diff
Author: Shengchen Kan
Date: 2024-06-25T09:25:32+08:00
New Revision: 8ad32ce7382bb8d630a3d4d93d1e1f00f8e2bd0e
URL:
https://github.com/llvm/llvm-project/commit/8ad32ce7382bb8d630a3d4d93d1e1f00f8e2bd0e
DIFF:
https://github.com/llvm/llvm-project/commit/8ad32ce7382bb8d630a3d4d93d1e1f00f8e2bd0e.diff
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/113402
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https://github.com/KanRobert commented:
LGTM
https://github.com/llvm/llvm-project/pull/109598
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https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 88cbdf9765e42dee7d2b050dcf8a20a08b4b148f Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/7] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
KanRobert wrote:
Ping @MaskRay ?
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/llvm/llvm-project/pull/106681
>From 88cbdf9765e42dee7d2b050dcf8a20a08b4b148f Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/8] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert edited
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KanRobert wrote:
Passed the validation of cpu2017 on intel sde w/ this patch + APX features.
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/KanRobert closed
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/116737
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https://github.com/KanRobert closed
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/120061
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KanRobert wrote:
> We also change -mno-avx10.[1,2]-512 to alias of 256 bit options to disable
> both 256 and 512 instructions.
Why this?
https://github.com/llvm/llvm-project/pull/124511
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KanRobert wrote:
> Introduce an option (-mapx-relax-relocations) to control the emission of the
> new APX relocations. It's off by default to keep backward compatibility with
> old version of ld and other linkers without APX support. And EGPR and NDD are
> also suppressed to avoid the instruct
https://github.com/KanRobert approved this pull request.
https://github.com/llvm/llvm-project/pull/137450
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KanRobert wrote:
> Any comments?
Still not understand the requirement...
https://github.com/llvm/llvm-project/pull/136660
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KanRobert wrote:
> > > Introduce an option (-mapx-relax-relocations) to control the emission of
> > > the new APX relocations. It's off by default to keep backward
> > > compatibility with old version of ld and other linkers without APX
> > > support. And EGPR and NDD are also suppressed to av
KanRobert wrote:
> Suppress EGPR/NDD instructions for relocations to avoid APX relocation types
> emitted. This is to keep backward compatibility with old version of ld and
> other linkers without APX support. If there are APX relocation types, old
> version of linkers would raise "unsupported
KanRobert wrote:
> > > Suppress EGPR/NDD instructions for relocations to avoid APX relocation
> > > types emitted. This is to keep backward compatibility with old version of
> > > ld and other linkers without APX support. If there are APX relocation
> > > types, old version of linkers would ra
@@ -1257,6 +1259,26 @@ inline bool isX86_64ExtendedReg(MCRegister Reg) {
return false;
}
+inline const TargetRegisterClass *
+constrainRegClassToNonRex2(const TargetRegisterClass *RC) {
KanRobert wrote:
It seems it's not appropriate place. X86BaseInfo is us
https://github.com/KanRobert approved this pull request.
https://github.com/llvm/llvm-project/pull/136660
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@@ -6679,8 +6679,13 @@ def mapx_features_EQ : CommaJoined<["-"],
"mapx-features=">, Group,
Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">, Visibility<[ClangOption,
CLOption, FlangOption]>;
def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
HelpTex
@@ -135,3 +135,53 @@
void f(void) {
}
+
+
+// RUN: not %clang_cl -### --target=i386 -mapx-features=ndd %s 2>&1 |
FileCheck --check-prefix=NON-APX %s
+// RUN: not %clang_cl -### --target=i386 -mapxf %s 2>&1 | FileCheck
--check-prefix=NON-APX %s
+// RUN: %clang_cl -### --targe
@@ -6679,8 +6679,13 @@ def mapx_features_EQ : CommaJoined<["-"],
"mapx-features=">, Group,
Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">, Visibility<[ClangOption,
CLOption, FlangOption]>;
def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
HelpTex
https://github.com/KanRobert approved this pull request.
https://github.com/llvm/llvm-project/pull/140874
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https://github.com/KanRobert approved this pull request.
https://github.com/llvm/llvm-project/pull/141486
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