[llvm] [clang] [X86][WIP] Use vXi1 for `k` constraint in inline asm (PR #77733)

https://github.com/phoebewang ready_for_review https://github.com/llvm/llvm-project/pull/77733 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)

https://github.com/phoebewang edited https://github.com/llvm/llvm-project/pull/77733 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[lldb] [openmp] [clang] [clang-tools-extra] [lld] [libunwind] [mlir] [llvm] [flang] [compiler-rt] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

@@ -1363,6 +1363,14 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) { MachineBasicBlock *Pred = *(MBB->pred_end()-1); Pred->ReplaceUsesOfBlockWith(MBB, &*FallThrough); } + // Add rest successors of MBB to successors of FallThrough. Those

[compiler-rt] [flang] [openmp] [clang-tools-extra] [mlir] [clang] [lldb] [llvm] [lld] [libunwind] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

@@ -1624,6 +1632,15 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) { } else { DidChange = true; PMBB->ReplaceUsesOfBlockWith(MBB, CurTBB); + // Add rest successors of MBB to successors of CurTBB. Those +

[llvm] [flang] [lld] [compiler-rt] [lldb] [libunwind] [mlir] [clang-tools-extra] [clang] [openmp] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/77608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] f5d781d - [X86] Support `_Float16` on SSE2 and up

Author: Phoebe Wang Date: 2022-06-27T21:37:30+08:00 New Revision: f5d781d6273cc56dd8b44ee9e4cfb2ae5579bb04 URL: https://github.com/llvm/llvm-project/commit/f5d781d6273cc56dd8b44ee9e4cfb2ae5579bb04 DIFF: https://github.com/llvm/llvm-project/commit/f5d781d6273cc56dd8b44ee9e4cfb2ae5579bb04.diff L

[clang] 527ef8c - Reland "[X86] Support `_Float16` on SSE2 and up"

Author: Phoebe Wang Date: 2022-06-28T14:38:56+08:00 New Revision: 527ef8ca981e88a35758c0e4143be6853ea26dfc URL: https://github.com/llvm/llvm-project/commit/527ef8ca981e88a35758c0e4143be6853ea26dfc DIFF: https://github.com/llvm/llvm-project/commit/527ef8ca981e88a35758c0e4143be6853ea26dfc.diff L

[clang] abeeae5 - [X86] Support `_Float16` on SSE2 and up

Author: Phoebe Wang Date: 2022-06-30T17:21:37+08:00 New Revision: abeeae570efff38dceccf68f5352809c58ffdda2 URL: https://github.com/llvm/llvm-project/commit/abeeae570efff38dceccf68f5352809c58ffdda2 DIFF: https://github.com/llvm/llvm-project/commit/abeeae570efff38dceccf68f5352809c58ffdda2.diff L

[clang] cd26190 - [X86][regcall] Support passing / returning structures

Author: Phoebe Wang Date: 2022-03-29T11:29:57+08:00 New Revision: cd26190a10fceb6e1472fabcd9e1736f62f078c4 URL: https://github.com/llvm/llvm-project/commit/cd26190a10fceb6e1472fabcd9e1736f62f078c4 DIFF: https://github.com/llvm/llvm-project/commit/cd26190a10fceb6e1472fabcd9e1736f62f078c4.diff L

[clang] 6f867f9 - [X86] Support ``-mindirect-branch-cs-prefix`` for call and jmp to indirect thunk

Author: Phoebe Wang Date: 2022-08-04T15:12:15+08:00 New Revision: 6f867f9102838ebe314c1f3661fdf95700386e5a URL: https://github.com/llvm/llvm-project/commit/6f867f9102838ebe314c1f3661fdf95700386e5a DIFF: https://github.com/llvm/llvm-project/commit/6f867f9102838ebe314c1f3661fdf95700386e5a.diff L

[clang] e4888a3 - [X86][BF16] Enable __bf16 for x86 targets.

Author: Freddy Ye Date: 2022-08-10T09:00:47+08:00 New Revision: e4888a37d36780872d685c68ef8b26b2e14d6d39 URL: https://github.com/llvm/llvm-project/commit/e4888a37d36780872d685c68ef8b26b2e14d6d39 DIFF: https://github.com/llvm/llvm-project/commit/e4888a37d36780872d685c68ef8b26b2e14d6d39.diff LOG

[clang] 3210360 - [Inline-asm] Add diagnosts for unsupported inline assembly arguments

Author: Phoebe Wang Date: 2022-03-23T11:25:19+08:00 New Revision: 32103608fc073700f04238872d8b22655ddec3fb URL: https://github.com/llvm/llvm-project/commit/32103608fc073700f04238872d8b22655ddec3fb DIFF: https://github.com/llvm/llvm-project/commit/32103608fc073700f04238872d8b22655ddec3fb.diff L

[clang] 3e19ba3 - [X86][MS] Add 80bit long double support for Windows

Author: Phoebe Wang Date: 2022-02-14T13:32:29+08:00 New Revision: 3e19ba36fca9fa0b6aba0de2767f26dfd463cb5a URL: https://github.com/llvm/llvm-project/commit/3e19ba36fca9fa0b6aba0de2767f26dfd463cb5a DIFF: https://github.com/llvm/llvm-project/commit/3e19ba36fca9fa0b6aba0de2767f26dfd463cb5a.diff L

[clang] db1cec3 - [X86] Fix CodeGen Module Flag for -mibt-seal

Author: Joao Moreira Date: 2022-04-29T15:37:28+08:00 New Revision: db1cec371c00722ce42683e0dc8a2021186332c5 URL: https://github.com/llvm/llvm-project/commit/db1cec371c00722ce42683e0dc8a2021186332c5 DIFF: https://github.com/llvm/llvm-project/commit/db1cec371c00722ce42683e0dc8a2021186332c5.diff

[clang] b540ee5 - [X86] Fix redundant `%s` in RUN command. NFC

Author: Phoebe Wang Date: 2022-05-04T20:29:50+08:00 New Revision: b540ee540266f42b238e683c775c32a10c184ab5 URL: https://github.com/llvm/llvm-project/commit/b540ee540266f42b238e683c775c32a10c184ab5 DIFF: https://github.com/llvm/llvm-project/commit/b540ee540266f42b238e683c775c32a10c184ab5.diff L

[clang] 2d18a86 - [X86] Fix uninitialized variable warnings in cetintrin.h reported by #55224

Author: Phoebe Wang Date: 2022-05-04T21:12:12+08:00 New Revision: 2d18a86d14a936798a34b10d4b951465b7f0527f URL: https://github.com/llvm/llvm-project/commit/2d18a86d14a936798a34b10d4b951465b7f0527f DIFF: https://github.com/llvm/llvm-project/commit/2d18a86d14a936798a34b10d4b951465b7f0527f.diff L

[clang] aa25b55 - [X86] Add `void` to void function. NFC

Author: Phoebe Wang Date: 2022-05-05T10:58:46+08:00 New Revision: aa25b55bde87501f72346704136951834140bda8 URL: https://github.com/llvm/llvm-project/commit/aa25b55bde87501f72346704136951834140bda8 DIFF: https://github.com/llvm/llvm-project/commit/aa25b55bde87501f72346704136951834140bda8.diff L

[clang] [Headers][X86] Add rounding and exception notes to conversions (PR #83447)

https://github.com/phoebewang approved this pull request. Looks great, thanks! https://github.com/llvm/llvm-project/pull/83447 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -0,0 +1,247 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=i686 --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 --reloc

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/8] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/8] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang closed https://github.com/llvm/llvm-project/pull/83136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86_64] fix empty structure vaarg in c++ (PR #77907)

@@ -3014,6 +3014,11 @@ Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE, /*isNamedArg*/false); + // Empty records are ignored for parameter pas

[clang] [X86_64] fix empty structure vaarg in c++ (PR #77907)

phoebewang wrote: Checked both pr77036.cpp and pr77036.c get the same result, so looks like a right fix. But I want to wait @efriedma-quic to sign off. https://github.com/llvm/llvm-project/pull/77907 ___ cfe-commits mailing list cfe-commits@lists.llvm

[clang] [X86][Headers] Specify result of NaN comparisons (PR #85862)

@@ -207,6 +207,8 @@ _mm256_div_ps(__m256 __a, __m256 __b) /// Compares two 256-bit vectors of [4 x double] and returns the greater ///of each pair of values. /// +///If either value in a comparison is NaN, returns the value from \a __b. phoebewang wrote

[clang] [X86][Headers] Specify result of NaN comparisons (PR #85862)

https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/85862 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Win32][ELF] Make CodeView a DebugInfoFormat only for COFF format (PR #87149)

https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/87149 We have many problems to use CodeView for a win32-elf target, e.g., #87140 and `error: .seh_* directives are not supported on this target`. Fixes: #87140 >From 745b2acb9dafbb54b00353f71dee464b3617c13a Mon Se

[clang] [Win32][ELF] Make CodeView a DebugInfoFormat only for COFF format (PR #87149)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/87149 >From 16fea4659909423319f0107b2a4d5bcc31185299 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Sat, 30 Mar 2024 17:29:06 +0800 Subject: [PATCH] [Win32][ELF] Make CodeView a DebugInfoFormat only for COFF form

[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)

@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) { Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1); Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1); Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1); + Feat

[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)

https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/80815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)

@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) { Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1); Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1); Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1); + Feat

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -0,0 +1,165 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-pc-linu

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang deleted https://github.com/llvm/llvm-project/pull/83136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/5] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/6] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/6] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -0,0 +1,165 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-pc-linu

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -18515,20 +18515,20 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { return LowerGlobalOrExternal(Op, DAG, /*ForCall=*/false); } -static SDValue -GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, - SDValue *InG

[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)

@@ -34,6 +34,60 @@ __m128 test_mm_andnot_ps(__m128 A, __m128 B) { return _mm_andnot_ps(A, B); } +__m128 test_mm_cmp_ps_eq_oq(__m128 a, __m128 b) { + // CHECK-LABEL: test_mm_cmp_ps_eq_oq + // CHECK: fcmp oeq <4 x float> %{{.*}}, %{{.*}} + return _mm_cmp_ps(a, b, _CMP_EQ_OQ

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

phoebewang wrote: > I assume that's what you're doing in the place I asked for a comment is > trying to avoid redundantly generating TLSDESC accesses for > _TLS_MODULE_BASE_. I see that we don't generate multiple accesses for > _TLS_MODULE_BASE_ in the test cases, but I thought that was only s

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/7] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -0,0 +1,165 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-pc-linu

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -18522,13 +18522,21 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SDLoc dl(GA); - SDValue TGA = DAG.getTargetGlobalAdd

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -18543,7 +18552,19 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, MFI.setHasCalls(true); SDValue Glue = Chain.getValue(1); - return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue); + SDValue Ret = DAG.getCopyFromReg(Chain, dl, ReturnRe

[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)

https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Add rounding and exception notes to conversions (PR #83447)

@@ -1405,11 +1413,12 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS _mm_cvtss_sd(__m128d __a, /// Converts the two double-precision floating-point elements of a ///128-bit vector of [2 x double] into two signed 32-bit integer values, -///returned in the lower 64 bits

[clang] [Headers][X86] Add rounding and exception notes to conversions (PR #83447)

@@ -1405,11 +1413,12 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS _mm_cvtss_sd(__m128d __a, /// Converts the two double-precision floating-point elements of a ///128-bit vector of [2 x double] into two signed 32-bit integer values, -///returned in the lower 64 bits

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

phoebewang wrote: Gentle ping~ https://github.com/llvm/llvm-project/pull/83136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/83136 None >From 421a5e4c0a6d7beda71118a36650e72c3d6f2377 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH] [X86] Add Support for X86 TLSDESC Relocations --- clang/

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH] [X86] Add Support for X86 TLSDESC Relocations --- clang/lib/Dr

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/2] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -18515,17 +18515,17 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { return LowerGlobalOrExternal(Op, DAG, /*ForCall=*/false); } -static SDValue -GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, - SDValue *InG

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -0,0 +1,165 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X86 phoebewang wrote: Done

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -0,0 +1,165 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-pc-linu

[clang] [Headers][X86] Add specific results to comparisons (PR #83316)

https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/83316 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/3] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

@@ -0,0 +1,165 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-pc-linu

[clang] [Headers][X86] Add rounding and exception notes to conversions (PR #83447)

@@ -2180,7 +2180,8 @@ _mm256_cvtepi32_pd(__m128i __a) return (__m256d)__builtin_convertvector((__v4si)__a, __v4df); } -/// Converts a vector of [8 x i32] into a vector of [8 x float]. +/// Converts a vector of [8 x i32] into a vector of [8 x float]. Rounds inexact +///re

[clang] [Headers][X86] Add rounding and exception notes to conversions (PR #83447)

@@ -2211,7 +2213,12 @@ _mm256_cvtpd_ps(__m256d __a) return (__m128)__builtin_ia32_cvtpd2ps256((__v4df) __a); } -/// Converts a vector of [8 x float] into a vector of [8 x i32]. +/// Converts a vector of [8 x float] into a vector of [8 x i32]. Rounds inexact +///results a

[clang] [lld] [llvm] [X86] Use generic CPU tuning when tune-cpu is empty (PR #83631)

phoebewang wrote: This is a turbulent change to both upstream and downstream tests without any profit as far as I can tell. I did a similar change for 64-bit a few years ago: https://reviews.llvm.org/D129647 In comparison, this patch is not to solve a specific problem. It should not show any

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

phoebewang wrote: Ping~ https://github.com/llvm/llvm-project/pull/83136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86] Add Support for X86 TLSDESC Relocations (PR #83136)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/83136 >From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Tue, 27 Feb 2024 22:16:38 +0800 Subject: [PATCH 1/4] [X86] Add Support for X86 TLSDESC Relocations --- clang/li

[clang] [llvm] Adding support of AMDLIBM vector library (PR #78560)

https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/78560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[mlir] [clang] [llvm] [X86] Stop custom-widening v2f32 = fpext v2bf16 (PR #80106)

@@ -32815,10 +32815,10 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, // No other ValueType for FP_EXTEND should reach this point. assert(N->getValueType(0) == MVT::v2f32 && "Do not know how to legalize this Node"); -if (!Subtarget.hasFP16() ||

[compiler-rt] [clang] [llvm] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)

@@ -139,20 +139,77 @@ enum ProcessorFeatures { FEATURE_AVX512BITALG, FEATURE_AVX512BF16, FEATURE_AVX512VP2INTERSECT, + FEATURE_3DNOW, + FEATURE_ADX = 40, + FEATURE_CLDEMOTE = 42, phoebewang wrote: Why do we skip some of features? https://github.com/l

[llvm] [clang] [compiler-rt] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)

@@ -139,20 +139,79 @@ enum ProcessorFeatures { FEATURE_AVX512BITALG, FEATURE_AVX512BF16, FEATURE_AVX512VP2INTERSECT, + // Below Features has many missings comparing to gcc, it's because gcc has + // some LLVM doesn't include, e.g. FEATURE_ABM, FEATURE_HLE, ... + FEATUR

[compiler-rt] [llvm] [clang] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)

@@ -139,20 +139,77 @@ enum ProcessorFeatures { FEATURE_AVX512BITALG, FEATURE_AVX512BF16, FEATURE_AVX512VP2INTERSECT, + FEATURE_3DNOW, + FEATURE_ADX = 40, + FEATURE_CLDEMOTE = 42, phoebewang wrote: ABM is a AMD specific feature https://en.wikipedia.or

[clang] [X86] [iamcu] Fix wrong alignment value for attr (aligned) with -miamcu (PR #80401)

https://github.com/phoebewang edited https://github.com/llvm/llvm-project/pull/80401 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] [iamcu] Fix wrong alignment value for attr (aligned) with -miamcu (PR #80401)

https://github.com/phoebewang approved this pull request. LGTM with one nit. https://github.com/llvm/llvm-project/pull/80401 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] [iamcu] Fix wrong alignment value for attr (aligned) with -miamcu (PR #80401)

@@ -1,4 +1,12 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin9 -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple i586-intel-elfiamcu -fsyntax-only -verify %s + +#ifdef __iamcu +// expected-no-diagnostics +struct dummy { int x __attribute__((aligned)); }; +int m0[__alignof__

[llvm] [clang-tools-extra] [compiler-rt] [clang] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)

@@ -139,20 +139,79 @@ enum ProcessorFeatures { FEATURE_AVX512BITALG, FEATURE_AVX512BF16, FEATURE_AVX512VP2INTERSECT, + // Below Features has many missings comparing to gcc, it's because gcc has + // some LLVM doesn't include, e.g. FEATURE_ABM, FEATURE_HLE, ... + FEATUR

[llvm] [clang-tools-extra] [compiler-rt] [clang] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)

@@ -139,20 +139,88 @@ enum ProcessorFeatures { FEATURE_AVX512BITALG, FEATURE_AVX512BF16, FEATURE_AVX512VP2INTERSECT, - - FEATURE_CMPXCHG16B = 46, - FEATURE_F16C = 49, + // FIXME: Below Features has some missings comparing to gcc, it's because gcc + // has some not one

[clang] [compiler-rt] [clang-tools-extra] [llvm] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)

@@ -217,10 +217,11 @@ enum ProcessorFeatures { FEATURE_SM3, FEATURE_SHA512, FEATURE_SM4, - // FEATURE_APX_F, - FEATURE_USERMSR = 112, - // FEATURE_AVX10_1_256, - // FEATURE_AVX10_1_512, + //FIXME: gcc used string "apxf" instead of "egpr" phoebewang w

[compiler-rt] [clang-tools-extra] [llvm] [clang] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)

@@ -217,8 +217,7 @@ enum ProcessorFeatures { FEATURE_SM3, FEATURE_SHA512, FEATURE_SM4, - //FIXME: gcc used string "apxf" instead of "egpr" - FEATURE_EGPR, + // FEATURE_APXF, FEATURE_USERMSR, phoebewang wrote: You need to change the number then. ht

[compiler-rt] [clang-tools-extra] [llvm] [clang] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)

https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/79086 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)

@@ -211,7 +214,11 @@ /* Features in %edx for leaf 7 sub-leaf 1 */ #define bit_AVXVNNIINT8 0x0010 #define bit_AVXNECONVERT 0x0020 +#define bit_AMXCOMPLEX0x0100 +#define bit_AVXVNNIINT16 0x0400 #define bit_PREFETCHI 0x4000 +#define bit_USERMSR

[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)

@@ -211,7 +214,11 @@ /* Features in %edx for leaf 7 sub-leaf 1 */ #define bit_AVXVNNIINT8 0x0010 #define bit_AVXNECONVERT 0x0020 +#define bit_AMXCOMPLEX0x0100 +#define bit_AVXVNNIINT16 0x0400 #define bit_PREFETCHI 0x4000 +#define bit_USERMSR

[llvm] [clang] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

@@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=i686 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64 < %s | FileCheck %s + +@var = external dso_local global i32, align 4 + +define dso_local void @test() { +; CHEC

[llvm] [clang] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

@@ -56966,6 +56965,17 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, } return; } + case 'W': { +assert(Constraint[1] == 's'); +if (const auto *GA = dyn_cast(Op)) { + Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op

[llvm] [clang] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

@@ -5336,6 +5336,7 @@ X86: operand in a SSE register. If AVX is also enabled, can also be a 256-bit vector operand in an AVX register. If AVX-512 is also enabled, can also be a 512-bit vector operand in an AVX512 register. Otherwise, an error. +- ``Ws``: A symbolic refere

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/77925 None >From cc0f2b24299bdfc9216ee87ab1aba08707f95503 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Fri, 12 Jan 2024 21:29:50 +0800 Subject: [PATCH] [AVX10][Doc] Add documentation about AVX10 options and the

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/77925 >From cc0f2b24299bdfc9216ee87ab1aba08707f95503 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Fri, 12 Jan 2024 21:29:50 +0800 Subject: [PATCH 1/2] [AVX10][Doc] Add documentation about AVX10 options and thei

[clang] [llvm] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)

phoebewang wrote: > Should we add test coverage for the gpr <-> mask transfers? Is the concern about existing BC files using gpr? It's covered by existing test case, e.g., function `@a` in pr41678.ll We don't remove the iN type support in X86ISelLowering.cpp, but add extra vXi1 support. https

[clang-tools-extra] [libcxx] [clang] [flang] [lldb] [llvm] [mlir] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

@@ -5336,6 +5336,7 @@ X86: operand in a SSE register. If AVX is also enabled, can also be a 256-bit vector operand in an AVX register. If AVX-512 is also enabled, can also be a 512-bit vector operand in an AVX512 register. Otherwise, an error. +- ``Ws``: A symbolic refere

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/77925 >From cc0f2b24299bdfc9216ee87ab1aba08707f95503 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Fri, 12 Jan 2024 21:29:50 +0800 Subject: [PATCH 1/3] [AVX10][Doc] Add documentation about AVX10 options and thei

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

@@ -3963,6 +3963,60 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL +`Intel AVX10 ISA

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

@@ -3963,6 +3963,60 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL +`Intel AVX10 ISA

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

@@ -3963,6 +3963,60 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL +`Intel AVX10 ISA

[clang] [X86_64] fix empty structure vaarg in c++ (PR #77907)

@@ -2989,6 +2989,11 @@ static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF, // an 8 byte boundary. uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8; + + if (isEmptyRecord(CGF.getContext(), Ty, true)) { +SizeInBytes = 0; + } + -

[clang] [X86_64] fix empty structure vaarg in c++ (PR #77907)

phoebewang wrote: I checked it locally, the patch doesn't fix the reported problem: ``` $ clang pr77036.cpp && ./a.out -nan Fail ``` https://github.com/llvm/llvm-project/pull/77907 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.l

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

@@ -3963,6 +3963,60 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL +`Intel AVX10 ISA

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

phoebewang wrote: > LGTM. Thanks! Thanks @e-kud ! https://github.com/llvm/llvm-project/pull/77925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/phoebewang closed https://github.com/llvm/llvm-project/pull/77925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [lldb] [clang-tools-extra] [llvm] [compiler-rt] [libc] [libcxx] [mlir] [flang] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

https://github.com/phoebewang approved this pull request. LGTM with some nits. https://github.com/llvm/llvm-project/pull/77886 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[flang] [libc] [clang-tools-extra] [mlir] [clang] [compiler-rt] [lldb] [libcxx] [llvm] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

https://github.com/phoebewang edited https://github.com/llvm/llvm-project/pull/77886 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[mlir] [flang] [llvm] [lldb] [compiler-rt] [libc] [libcxx] [clang] [clang-tools-extra] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

@@ -1418,6 +1418,14 @@ bool X86TargetInfo::validateAsmConstraint( case 'O': Info.setRequiresImmediate(0, 127); return true; + case 'W': +switch (*++Name) { +default: + return false; +case 's': + Info.setAllowsRegister(); phoebew

[llvm] [clang] [lldb] [libcxx] [compiler-rt] [libc] [mlir] [flang] [clang-tools-extra] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

@@ -130,3 +130,7 @@ void pr40890(void) { __asm__ __volatile__("\n#define BEEF abcd%0\n" : : "n"((int*)0xdeadbeef)); #endif } + +void test_W(int i) { + asm("" : : "Wd"(test_W)); // expected-error{{invalid input constraint 'Wd' in asm}} phoebewang wrote:

[libc] [mlir] [clang] [compiler-rt] [libcxx] [clang-tools-extra] [flang] [llvm] [lldb] [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (PR #77886)

@@ -130,3 +130,7 @@ void pr40890(void) { __asm__ __volatile__("\n#define BEEF abcd%0\n" : : "n"((int*)0xdeadbeef)); #endif } + +void test_W(int i) { + asm("" : : "Wd"(test_W)); // expected-error{{invalid input constraint 'Wd' in asm}} phoebewang wrote:

[clang] [llvm] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)

phoebewang wrote: > Why not return `i32` for 64-bit mask in 32-bit mode? You mean in two `i32` registers? The problem is the inline asm constraint has 1:1 map with physical register except corner cases. And represent a `k` constraint into two GPR registers is inefficient. https://github.com/l

[llvm] [clang] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)

phoebewang wrote: > > > Why not return `i32` for 64-bit mask in 32-bit mode? > > > > > > You mean in two `i32` registers? The problem is the inline asm constraint > > has 1:1 map with physical register except corner cases. And represent a `k` > > constraint into two GPR registers is inefficie

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