================
@@ -139,20 +139,79 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
+ // Below Features has many missings comparing to gcc, it's because gcc has
+ // some LLVM doesn't include, e.g. FEATURE_ABM, FEATURE_HLE, ...
+ FEATURE_3DNOW,
+ FEATURE_ADX = 40,
+ FEATURE_CLDEMOTE = 42,
+ FEATURE_CLFLUSHOPT,
+ FEATURE_CLWB,
+ FEATURE_CLZERO,
+ FEATURE_CMPXCHG16B,
+
+ FEATURE_ENQCMD = 48,
+ FEATURE_F16C,
+ FEATURE_FSGSBASE,
----------------
phoebewang wrote:
Oh, you are right. The 2 features map to two CPUID bits in SDM
> Bit 07: CET_SS. Supports CET shadow stack features if 1. Processors that set
> this bit define bits 1:0
> of the IA32_U_CET and IA32_S_CET MSRs. Enumerates support for the following
> MSRs: IA32_INTERRUPT_SPP_TABLE_ADDR, IA32_PL3_SSP, IA32_PL2_SSP,
> IA32_PL1_SSP, and IA32_PL0_SSP.
> Bit 20: CET_IBT. Supports CET indirect branch tracking features if 1.
> Processors that set this bit
> define bits 5:2 and bits 63:10 of the IA32_U_CET and IA32_S_CET MSRs.
https://github.com/llvm/llvm-project/pull/79086
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