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https://github.com/llvm/llvm-project/pull/93777
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FreddyLeaf wrote:
Sorry, I was OOO, thanks for the fix!
https://github.com/llvm/llvm-project/pull/92338
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@@ -248,6 +248,10 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name));
}
+ llvm::StringSet<> SubFeaturesOfAPX = {"egpr", "push2pop2", "ppx", "ndd",
+
@@ -309,8 +309,8 @@
// HRESET: "-target-feature" "+hreset"
// NO-HRESET: "-target-feature" "-hreset"
-// RUN: %clang --target=i386 -march=i386 -muintr %s -### 2>&1 | FileCheck
-check-prefix=UINTR %s
-// RUN: %clang --target=i386 -march=i386 -mno-uintr %s -### 2>&1 | FileCheck
@@ -248,6 +248,10 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name));
}
+ llvm::StringSet<> SubFeaturesOfAPX = {"egpr", "push2pop2", "ppx", "ndd",
+
@@ -175,8 +175,6 @@ X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",
34)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect", 35)
// Below Features has some missings comparing to gcc, it's because gcc has some
// not one-to-one mapped in llvm.
-X86_FEATURE_
@@ -175,8 +175,6 @@ X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",
34)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect", 35)
// Below Features has some missings comparing to gcc, it's because gcc has some
// not one-to-one mapped in llvm.
-X86_FEATURE_
@@ -175,8 +175,6 @@ X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",
34)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect", 35)
// Below Features has some missings comparing to gcc, it's because gcc has some
// not one-to-one mapped in llvm.
-X86_FEATURE_
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https://github.com/llvm/llvm-project/pull/99352
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@@ -0,0 +1,1054 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64 -target-feature +avx10.2-512 -emit-llvm -o -
-Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-
@@ -14836,6 +14837,9 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned
BuiltinID,
case X86::BI__builtin_ia32_vfmaddph512_mask:
case X86::BI__builtin_ia32_vfmaddph512_maskz:
case X86::BI__builtin_ia32_vfmaddph512_mask3:
+ case X86::BI__builtin_ia32_vfmaddnepbh128:
+
@@ -211,6 +211,12 @@ def X86CmpMaskCC :
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
SDTCisVec<1>, SDTCisSameAs<2, 1>,
SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
+
+def X86CmpMaskCC_Int :
+ SDTypeProfile<1
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
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@@ -0,0 +1,565 @@
+/*===--- avx10_2_512bf16intrin.h - AVX10-BF16 intrinsics -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache
@@ -0,0 +1,1054 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64 -target-feature +avx10.2-512 -emit-llvm -o -
-Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-
@@ -7219,3 +7219,413 @@ def int_x86_avx10_mask_vcvtneph2hf8s512 :
ClangBuiltin<"__builtin_ia32_vcvtneph2
DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v32f16_ty, llvm_v32i8_ty,
llvm_i32_ty],
[IntrNoMem]>;
}
+
+//===
@@ -0,0 +1,565 @@
+/*===--- avx10_2_512bf16intrin.h - AVX10-BF16 intrinsics -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -147,11 +147,13 @@ set(x86_files
amxcomplexintrin.h
amxfp16intrin.h
amxintrin.h
+ avx10_2_512bf16intrin.h
avx10_2_512convertintrin.h
avx10_2_512minmaxintrin.h
avx10_2_512niintrin.h
avx10_2_512satcvtintrin.h
avx10_2convertintrin.h
+ avx10_2bf16intrin.h
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
FreddyLeaf wrote:
> Should we add folding in X86InstrFMA3Info.cpp?
yes, addressed in
[b9e35f0](https://github.com/llvm/llvm-project/pull/101603/commits/b9e35f050d6319ebd8da3c0f4cf5399dd03b3915)
https://github.com/llvm/llvm-project/pull/101603
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FreddyLeaf wrote:
Thanks for the fix!
https://github.com/llvm/llvm-project/pull/98426
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None
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH] [X86][CFE] Support EGPR in inline assembly.
---
clang/lib/B
https://github.com/FreddyLeaf converted_to_draft
https://github.com/llvm/llvm-project/pull/91323
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>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH 1/2] [X86][CFE] Support EGPR in inline assembly.
---
clang/lib/Bas
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/91323
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH 1/3] [X86][CFE] Support EGPR in inline assembly.
---
clang/lib/Bas
https://github.com/FreddyLeaf ready_for_review
https://github.com/llvm/llvm-project/pull/91323
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@@ -1763,10 +1823,14 @@ void
X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl &Values) con
}
ArrayRef X86TargetInfo::getGCCRegNames() const {
+ if (HasEGPR)
+return llvm::ArrayRef(ExtendedGCCRegNames);
return llvm::ArrayRef(GCCRegNames);
FreddyLeaf
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
w
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/91323
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH 1/4] [X86][CFE] Support EGPR in inline assembly.
---
clang/lib/Bas
@@ -1763,10 +1823,14 @@ void
X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl &Values) con
}
ArrayRef X86TargetInfo::getGCCRegNames() const {
+ if (HasEGPR)
+return llvm::ArrayRef(ExtendedGCCRegNames);
return llvm::ArrayRef(GCCRegNames);
FreddyLeaf
@@ -83,8 +85,23 @@ const TargetInfo::AddlRegName AddlRegNames[] = {
{{"r13d", "r13w", "r13b"}, 43},
{{"r14d", "r14w", "r14b"}, 44},
{{"r15d", "r15w", "r15b"}, 45},
+{{"r16d", "r16w", "r16b"}, 165},
FreddyLeaf wrote:
it's the index of "r16" in G
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
w
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
t
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
b
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
>
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/91323
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH 1/5] [X86][CFE] Support EGPR in inline assembly.
---
clang/lib/Bas
FreddyLeaf wrote:
[a627464](https://github.com/llvm/llvm-project/pull/91323/commits/a627464ef0ed4e999dc52b6b2d445548b559fe8b)
https://github.com/llvm/llvm-project/pull/91323
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"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
>From 41fbc18c7a4a26b11bc4b772bbe2
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
I want to use
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
`mcmodel` mayb
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
pls notice tha
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FreddyLeaf wrote:
> Please put the corresponding GCC links for your description
done.
https://github.com/llvm/llvm-project/pull/92338
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>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/3] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
> Will the fea
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
SSELevel relie
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
> > > Will the
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/4] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
FreddyLeaf wrote:
ping for review
https://github.com/llvm/llvm-project/pull/92338
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>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/5] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
FreddyLeaf wrote:
[4d1ad30](https://github.com/llvm/llvm-project/pull/92338/commits/4d1ad3090416cda320c88f1ddc0937b5749e64b4)
moved but not merged. These two constraints will behavior different under
-mattr=+egpr.
https://github.com/llvm/llvm-project/pull/923
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/6] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
FreddyLeaf wrote:
> `
> [4087704](/llvm/llvm-project/pull/92338/commits/40877041618aa8f472f0da7cda06c21f4007a1ec)`
Thanks reminding. Added in 4087704, pls help review.
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
gcc recently formally removed knl/knm supports at trunk:
https://godbolt.org/z/nKvo1P48d
Per conclusion before in https://github.com/llvm/llvm-project/pull/75580, this
patch removed specific ISA supports of knl/knm while keep -march/tune support
https://github.com/llvm/llvm-p
https://github.com/FreddyLeaf ready_for_review
https://github.com/llvm/llvm-project/pull/92883
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>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/7] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
--check-prefix=EGPR
+; RUN: llc -mtriple=x86_64
@@ -23,7 +23,7 @@
br i1 %6, label %4, label %5, !llvm.loop !9
}
- attributes #0 = { nofree norecurse nosync nounwind uwtable writeonly
mustprogress "frame-pointer"="none" "min-legal-vector-width"="0"
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target
@@ -268,30 +268,6 @@ define void @gather_qps(<8 x i64> %ind, <8 x float> %src,
ptr %base, ptr %stbuf)
ret void
}
-declare void @llvm.x86.avx512.gatherpf.qps.512(i8, <8 x i64>, ptr , i32, i32);
FreddyLeaf wrote:
yes, this should be a bug before.
https://g
@@ -1,373 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
FreddyLeaf wrote:
scheduleinfo was removed. Now I think we should keep schedule info for these
instructions, will add back.
https://github.com/llvm/llvm-project/pul
@@ -8,16 +8,12 @@ target triple = "x86_64-unknown-linux-gnu"
define dso_local i32 @main() local_unnamed_addr #0 !dbg !7 {
entry:
tail call void @llvm.prefetch(ptr inttoptr (i64 291 to ptr), i32 0, i32 0,
i32 1), !dbg !9
- tail call void @llvm.x86.avx512.gatherpf.dpd.512(i8
@@ -1,373 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
FreddyLeaf wrote:
[13a0f8d](https://github.com/llvm/llvm-project/pull/92883/commits/13a0f8d87343fd1a6380a66b7986ad1ce34b06fc)
https://github.com/llvm/llvm-project/pu
FreddyLeaf wrote:
> Please note it in release notes.
[13a0f8d](https://github.com/llvm/llvm-project/pull/92883/commits/13a0f8d87343fd1a6380a66b7986ad1ce34b06fc)
https://github.com/llvm/llvm-project/pull/92883
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/8] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
@@ -139,6 +139,9 @@ Changes to the Windows Target
Changes to the X86 Backend
--
+- Removed knl/knm specific ISA lowerings: AVX512PF, AVX512ER, PREFETCHWT1,
FreddyLeaf wrote:
[3470095](https://github.com/llvm/llvm-project/pull/92883/com
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/92883
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@@ -58016,15 +58035,27 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
break;
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
+ if (Subtarget.useInlineAsmGPR32()) {
+if (VT == MVT::i8 || VT == MVT::i1)
+
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/93123
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FreddyLeaf wrote:
any idea on why `Labelling new pull requests / greeter (pull_request_target)`
is **skipped**? @phoebewang @RKSimon
https://github.com/llvm/llvm-project/pull/93136
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FreddyLeaf wrote:
> Not sure - CI checks aren't running either
Woops, I was thinking that is CI checks. I was just wondering for CI checks.
Now it's recovered. Thanks anyway!
https://github.com/llvm/llvm-project/pull/93136
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https://github.com/llvm/llvm-project/pull/93136
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/8] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
FreddyLeaf wrote:
ping @KanRobert
https://github.com/llvm/llvm-project/pull/92338
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@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
@@ -1819,7 +1819,7 @@ const StringMap sys::getHostCPUFeatures() {
Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) &&
HasAVXSave;
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
@@ -0,0 +1,83 @@
+/*=== avx10_2niintrin.h - AVX10.2 new instruction intrinsics ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apach
@@ -162,6 +162,9 @@ bool SemaX86::CheckBuiltinRoundingOrSAE(unsigned BuiltinID,
CallExpr *TheCall) {
case X86::BI__builtin_ia32_mulps512:
case X86::BI__builtin_ia32_subpd512:
case X86::BI__builtin_ia32_subps512:
+ case X86::BI__builtin_ia32_vaddpd256_round:
@@ -0,0 +1,24 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - |
FileCheck %s
+
FreddyLeaf wrote:
pls add i386 test.
https://github.com/llvm/llvm-project/pull/101
@@ -0,0 +1,105 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - |
FileCheck %s
+
FreddyLeaf wrote:
ditto
https://github.com/llvm/llvm-project/pull/101452
@@ -257,6 +257,8 @@ X86_FEATURE_COMPAT(USERMSR, "usermsr",
0)
X86_FEATURE_COMPAT(AVX10_1, "avx10.1-256", 36)
X86_FEATURE_COMPAT(AVX10_1_512, "avx10.1-512", 37)
X86_FEATURE (ZU, "zu")
+X86_FEATURE_COMPAT(
@@ -257,6 +257,8 @@ X86_FEATURE_COMPAT(USERMSR, "usermsr",
0)
X86_FEATURE_COMPAT(AVX10_1, "avx10.1-256", 36)
X86_FEATURE_COMPAT(AVX10_1_512, "avx10.1-512", 37)
X86_FEATURE (ZU, "zu")
+X86_FEATURE_COMPAT(
@@ -0,0 +1,24 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - |
FileCheck %s
+
FreddyLeaf wrote:
is `-flax-vector-conversions=none` required?
https://github.com/
@@ -0,0 +1,33 @@
+//===-- X86InstrAVX10.td - AVX10 Instruction Set ---*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
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