@@ -20,6 +20,11 @@
#include
#endif
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||
\
+defined(__UINTR__)
FreddyLeaf wrote:
3e32e495d8fa56ad3770769a5d4559ea0a41af96
https://github.com/llvm/llvm-project/pull/68944
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/68944
>From 2377ab2b9865d8f152996fd38f6b543767f8c2ae Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 11 Oct 2023 14:09:02 +0800
Subject: [PATCH 1/3] Add USER_MSR instructions.
For more details about this instru
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@@ -1249,6 +1249,18 @@ def ProcessorFeatures {
list ARLSFeatures =
!listconcat(SRFFeatures, ARLSAdditionalFeatures);
+ // Pantherlake
+ list PTLAdditionalFeatures = [FeaturePREFETCHI];
+ list PTLFeatures =
+!listconcat(ARLSFeatures, PTLAdditionalFeatures);
---
@@ -2538,6 +2544,9 @@
// CHECK_SRF_M32: #define __PCONFIG__ 1
// CHECK_SRF_M32: #define __PKU__ 1
// CHECK_SRF_M32: #define __POPCNT__ 1
+// CHECK_SRF_M32-NOT: #define __PREFETCHI__ 1
+// CHECK_ARLS_M32-NOT: #define __PREFETCHI__ 1
+// CHECK_PTL_M32: #define __PREFETCHI__ 1
---
@@ -2628,6 +2647,9 @@
// CHECK_SRF_M64: #define __PCONFIG__ 1
// CHECK_SRF_M64: #define __PKU__ 1
// CHECK_SRF_M64: #define __POPCNT__ 1
+// CHECK_SRF_M64-NOT: #define __PREFETCHI__ 1
+// CHECK_ARLS_M64-NOT: #define __PREFETCHI__ 1
+// CHECK_PTL_M64: #define __PREFETCHI__ 1
---
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/66310:
For *_stream_* series intrinsics.
>From 21157a0e3b4c4e4e2430752ef806148685a942a2 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Thu, 14 Sep 2023 09:17:39 +0800
Subject: [PATCH] [X86] Align 128/256 variants
https://github.com/FreddyLeaf review_requested
https://github.com/llvm/llvm-project/pull/66310
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FreddyLeaf wrote:
Here's the change for 512 variants before: https://reviews.llvm.org/D66786
https://github.com/llvm/llvm-project/pull/66310
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Author: Freddy Ye
Date: 2023-07-03T08:13:17+08:00
New Revision: b026c9eb1051c854ff13980cd30369f60b9a88c3
URL:
https://github.com/llvm/llvm-project/commit/b026c9eb1051c854ff13980cd30369f60b9a88c3
DIFF:
https://github.com/llvm/llvm-project/commit/b026c9eb1051c854ff13980cd30369f60b9a88c3.diff
LOG
Author: Freddy Ye
Date: 2023-07-05T17:32:00+08:00
New Revision: 7717c0071d7ce9f4ca7b1417f677bb0380171621
URL:
https://github.com/llvm/llvm-project/commit/7717c0071d7ce9f4ca7b1417f677bb0380171621
DIFF:
https://github.com/llvm/llvm-project/commit/7717c0071d7ce9f4ca7b1417f677bb0380171621.diff
LOG
Author: Freddy Ye
Date: 2023-07-07T13:47:33+08:00
New Revision: a10dccf2712fe4c9d90684626f510913bc6d1307
URL:
https://github.com/llvm/llvm-project/commit/a10dccf2712fe4c9d90684626f510913bc6d1307
DIFF:
https://github.com/llvm/llvm-project/commit/a10dccf2712fe4c9d90684626f510913bc6d1307.diff
LOG
Author: Freddy Ye
Date: 2022-11-29T15:08:17+08:00
New Revision: 67e253c35437b9fb38f968f60d54f203abecd634
URL:
https://github.com/llvm/llvm-project/commit/67e253c35437b9fb38f968f60d54f203abecd634
DIFF:
https://github.com/llvm/llvm-project/commit/67e253c35437b9fb38f968f60d54f203abecd634.diff
LOG
Author: Freddy Ye
Date: 2022-11-30T10:40:42+08:00
New Revision: 51679dc1c9d52ca906a739bafdd7be0041d7b3ce
URL:
https://github.com/llvm/llvm-project/commit/51679dc1c9d52ca906a739bafdd7be0041d7b3ce
DIFF:
https://github.com/llvm/llvm-project/commit/51679dc1c9d52ca906a739bafdd7be0041d7b3ce.diff
LOG
Author: Freddy Ye
Date: 2023-06-28T13:53:35+08:00
New Revision: 43baa5986c20aa510144c0de9b7782050ccba530
URL:
https://github.com/llvm/llvm-project/commit/43baa5986c20aa510144c0de9b7782050ccba530
DIFF:
https://github.com/llvm/llvm-project/commit/43baa5986c20aa510144c0de9b7782050ccba530.diff
LOG
Author: Freddy Ye
Date: 2023-06-29T13:30:13+08:00
New Revision: 548e08c3f635f72519d3bcadcc71cca7d31d1e6d
URL:
https://github.com/llvm/llvm-project/commit/548e08c3f635f72519d3bcadcc71cca7d31d1e6d
DIFF:
https://github.com/llvm/llvm-project/commit/548e08c3f635f72519d3bcadcc71cca7d31d1e6d.diff
LOG
Author: Freddy Ye
Date: 2023-06-30T13:19:15+08:00
New Revision: a9256a2e0450019aeb2dfcc3ad9fefb23d6d6f83
URL:
https://github.com/llvm/llvm-project/commit/a9256a2e0450019aeb2dfcc3ad9fefb23d6d6f83
DIFF:
https://github.com/llvm/llvm-project/commit/a9256a2e0450019aeb2dfcc3ad9fefb23d6d6f83.diff
LOG
Author: Freddy Ye
Date: 2023-06-30T14:14:31+08:00
New Revision: 3cf2f5c4cd512548c7eff7c167fb6d8d7b21aded
URL:
https://github.com/llvm/llvm-project/commit/3cf2f5c4cd512548c7eff7c167fb6d8d7b21aded
DIFF:
https://github.com/llvm/llvm-project/commit/3cf2f5c4cd512548c7eff7c167fb6d8d7b21aded.diff
LOG
Author: Freddy Ye
Date: 2023-04-06T13:19:44+08:00
New Revision: 847abddedca9ed2934e0c2386662ccb04ba4d298
URL:
https://github.com/llvm/llvm-project/commit/847abddedca9ed2934e0c2386662ccb04ba4d298
DIFF:
https://github.com/llvm/llvm-project/commit/847abddedca9ed2934e0c2386662ccb04ba4d298.diff
LOG
Author: Freddy Ye
Date: 2022-12-06T11:02:27+08:00
New Revision: def720726b73e0d7ab139376ab3ea955f25f4d89
URL:
https://github.com/llvm/llvm-project/commit/def720726b73e0d7ab139376ab3ea955f25f4d89
DIFF:
https://github.com/llvm/llvm-project/commit/def720726b73e0d7ab139376ab3ea955f25f4d89.diff
LOG
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/80636
>From b131b0971d5c38a29c954b37c0da8fb3177e5c92 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 5 Feb 2024 14:07:29 +0800
Subject: [PATCH 1/4] [X86] Support APXF to enable __builtin_cpu_supports.
---
clan
FreddyLeaf wrote:
After
[fa42b33](https://github.com/llvm/llvm-project/pull/80636/commits/fa42b33d62227bd88cc5d63431244d0caac1e286)
1. An error will be thrown out if compiling `__builtin_cpu_supports("egpr")`
2. __attribute__((__target__("apxf"))) is not supported in this patch, no
matter amend
FreddyLeaf wrote:
> You may also need to transfer "apxf" feature into subfeatures here
> https://github.com/llvm/llvm-project/blob/main/clang/lib/Basic/Targets/X86.cpp#L106
Thanks for pointing out! This looks like the change required by supporting
attribute((target("apxf"))). While that suppor
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/80636
>From b131b0971d5c38a29c954b37c0da8fb3177e5c92 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 5 Feb 2024 14:07:29 +0800
Subject: [PATCH 1/5] [X86] Support APXF to enable __builtin_cpu_supports.
---
clan
@@ -1845,6 +1845,12 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Fea
@@ -265,6 +265,7 @@ X86_MICROARCH_LEVEL(X86_64_BASELINE,"x86-64",
95)
X86_MICROARCH_LEVEL(X86_64_V2, "x86-64-v2",96)
X86_MICROARCH_LEVEL(X86_64_V3, "x86-64-v3",97)
X86_MICROARCH_LEVEL(X86_64_V4, "x86-64-v4",98)
+
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/80636
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@@ -219,6 +219,7 @@
#define bit_PREFETCHI 0x4000
#define bit_USERMSR 0x8000
#define bit_AVX10 0x0008
+#define bit_APXF 0x0020
FreddyLeaf wrote:
Done.
https://github.com/llvm/llvm-project/pull/80636
__
@@ -983,6 +983,8 @@ static void getAvailableFeatures(unsigned ECX, unsigned
EDX, unsigned MaxLeaf,
setFeature(FEATURE_USERMSR);
if (HasLeaf7Subleaf1 && ((EDX >> 19) & 1))
setFeature(FEATURE_AVX10_1_256);
+ if (HasLeaf7Subleaf1 && ((EDX >> 21) & 1))
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/80636
>From b131b0971d5c38a29c954b37c0da8fb3177e5c92 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 5 Feb 2024 14:07:29 +0800
Subject: [PATCH 1/6] [X86] Support APXF to enable __builtin_cpu_supports.
---
clan
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/80636
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@@ -265,6 +265,7 @@ X86_MICROARCH_LEVEL(X86_64_BASELINE,"x86-64",
95)
X86_MICROARCH_LEVEL(X86_64_V2, "x86-64-v2",96)
X86_MICROARCH_LEVEL(X86_64_V3, "x86-64-v3",97)
X86_MICROARCH_LEVEL(X86_64_V4, "x86-64-v4",98)
+
FreddyLeaf wrote:
ping
https://github.com/llvm/llvm-project/pull/80636
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FreddyLeaf wrote:
Thank you both for all of the review!
https://github.com/llvm/llvm-project/pull/80636
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@@ -153,7 +163,8 @@ const X86InstrFMA3Group *llvm::getFMA3Group(unsigned
Opcode, uint64_t TSFlags) {
((TSFlags & X86II::EncodingMask) == X86II::EVEX &&
((TSFlags & X86II::OpMapMask) == X86II::T8 ||
(TSF
@@ -205,7 +214,8 @@ bool X86ATTInstPrinter::printVecCompareInstr(const MCInst
*MI,
printwordmem(MI, CurOp--, OS);
else
printdwordmem(MI, CurOp--, OS);
- } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) {
+
@@ -205,7 +214,8 @@ bool X86ATTInstPrinter::printVecCompareInstr(const MCInst
*MI,
printwordmem(MI, CurOp--, OS);
else
printdwordmem(MI, CurOp--, OS);
- } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) {
+
@@ -200,6 +200,14 @@
#include
#endif
+#if !defined(__SCE__) || __has_feature(modules) || defined(__AVX10_2__)
+#include
FreddyLeaf wrote:
merge with other avx10_2 header files.
https://github.com/llvm/llvm-project/pull/102592
__
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/102592
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https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/103898
None
>From d5275ef5e6a4e34bdae6b9b505ba1aae3a9a2363 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 14 Aug 2024 19:45:21 +0800
Subject: [PATCH] [X86][MC] Remove CMPCCXADD's CondCode flavor.
---
clang/t
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https://github.com/llvm/llvm-project/pull/103898
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@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/103898
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@@ -2217,6 +2217,50 @@ TARGET_BUILTIN(__builtin_ia32_vcvttps2ibs512_mask,
"V16UiV16fV16UiUsIi", "nV:512
TARGET_BUILTIN(__builtin_ia32_vcvttps2iubs128_mask, "V4UiV4fV4UiUc",
"nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvttps2iubs256_mask, "V8UiV8fV8UiUcIi",
"nV:25
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/88343
Relate gcc patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-April/648789.html
>From 88e99b1f3f99140e13f7acb8e7e10162dc1694a0 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 10 Apr 2024 16:49:05 +080
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/88343
>From 88e99b1f3f99140e13f7acb8e7e10162dc1694a0 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 10 Apr 2024 16:49:05 +0800
Subject: [PATCH 1/2] [X86] Define __APX_F__ when APX is enabled.
Relate gcc patch:
@@ -954,6 +954,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__CCMP__");
if (HasCF)
Builder.defineMacro("__CF__");
+ if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
FreddyLeaf wrote:
4929d88
https://githu
https://github.com/FreddyLeaf closed
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https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/9] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
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@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+switch (Constraint[1]) {
+default:
+ break;
+case 'R':
+ if
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/10] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
--
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return
@@ -57660,6 +57668,19 @@ X86TargetLowering::getSingleConstraintMatchWeight(
break;
}
break;
+ case 'j':
+if (StringRef(Constraint).size() != 2)
+ break;
+switch (Constraint[1]) {
+default:
+ return CW_Invalid;
+case 'r':
+case 'R':
+
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/11] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
FreddyLeaf wrote:
81f58b6
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
81f58b6, pls review if I understand correctly.
https://github.com/llvm/llvm-project/pull/92338
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@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/12] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/92338
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@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
FreddyLeaf wrote:
I'll try. If so, we can refine l
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/13] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
FreddyLeaf wrote:
[e752556](https://github.com/llv
FreddyLeaf wrote:
[e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3)
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
[e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3)
https://github.com/llvm/llvm-project/pull/92338
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@@ -57999,13 +58020,25 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget.is64Bit()) {
if (VT == MVT::i8 || VT == MVT::i1)
- return std::m
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/13] [X86] Support EGPR for inline assembly.
"jR": explictly ena
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/93777
None
>From 7f5ca96930fe48617115e2403094e2724aa7b9cd Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Thu, 30 May 2024 15:20:18 +0800
Subject: [PATCH] Fix build warning for '[X86] Support EGPR for inline
assemb
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