================ @@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, } break; } + } else if (Constraint.size() == 2 && Constraint[0] == 'j') { + switch (Constraint[1]) { + default: + break; + case 'R': + if (VT == MVT::i8 || VT == MVT::i1) + return std::make_pair(0U, &X86::GR8RegClass); + if (VT == MVT::i16) + return std::make_pair(0U, &X86::GR16RegClass); + if (VT == MVT::i32 || VT == MVT::f32 || + (!VT.isVector() && !Subtarget.is64Bit())) + return std::make_pair(0U, &X86::GR32RegClass); ---------------- FreddyLeaf wrote:
addressed in [bf3a53c](https://github.com/llvm/llvm-project/pull/92338/commits/bf3a53c0b7fc1828572f771e4772d25062110dc0) https://github.com/llvm/llvm-project/pull/92338 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits