[clang] [llvm] [RISCV] Fix xmipscmov extension name (PR #135647)

https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/135647 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

https://github.com/djtodoro edited https://github.com/llvm/llvm-project/pull/130587 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D, CPUName == "mips64r5" || CPUName == "octeon" || CPUName == "octeon+", "-march=mips64r2", Flags); - addMultilibFlag(CPUName == "mips64r6",

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo { Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 }; - enum class CPU { P5600 }; + enum class CPU { P5600, I6400 }; djtodoro wrote: do we need "i6500" here as well

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo { Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 }; - enum class CPU { P5600 }; + enum class CPU { P5600, I6400 }; djtodoro wrote: So, we do not use this in this

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

https://github.com/djtodoro requested changes to this pull request. Thanks for working on this. https://github.com/llvm/llvm-project/pull/130587 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

@@ -238,13 +238,10 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", "MipsSubtarget::CPU::P5600", "The P5600 Processor", [FeatureMips32r5]>; +// I6500 is multicluster version of I6400. Both are based on s

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

@@ -47,14 +47,16 @@ bool MipsTargetInfo::processorSupportsGPR64() const { .Case("mips64r6", true) .Case("octeon", true) .Case("octeon+", true) + .Case("i6400", true) + .Case("i6500", true) .Default(false); } static constexpr llvm::StringLi

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

https://github.com/djtodoro created https://github.com/llvm/llvm-project/pull/134065 Add support for MipsTechnologies for RISC-V targets. >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/2] [

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

djtodoro wrote: > No tests? @topperc Added. https://github.com/llvm/llvm-project/pull/134065 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/3] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor --- clang/

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