https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/4] [CIR] Upstream global initialization for ComplexType
--
@@ -385,6 +385,13 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
break;
}
+ case Type::Complex: {
+const ComplexType *ct = cast(ty);
+mlir::Type elementTy = convertType(ct->getElementType());
AmrDeveloper wrote:
Thanks for your comment
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/14
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@@ -577,12 +577,31 @@ mlir::Attribute ConstantEmitter::tryEmitPrivate(const
APValue &value,
case APValue::Union:
cgm.errorNYI("ConstExprEmitter::tryEmitPrivate struct or union");
return {};
- case APValue::FixedPoint:
case APValue::ComplexInt:
- case APValue::Co
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141411
>From 12295ee3a5613d7473ab33a4579015a2217617a0 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sun, 25 May 2025 17:21:34 +0200
Subject: [PATCH 1/2] [CIR] Upstream ShuffleDynamicOp for VectorType
---
cla
@@ -1548,6 +1548,20 @@ OpFoldResult cir::VecExtractOp::fold(FoldAdaptor
adaptor) {
return elements[index];
}
+//===--===//
+// VecShuffleDynamicOp
+//===-
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/5] [CIR] Upstream global initialization for ComplexType
--
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/140125
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,s
@@ -54,10 +54,12 @@ namespace direct {
namespace {
/// If the given type is a vector type, return the vector's element type.
/// Otherwise return the given type unchanged.
-// TODO(cir): Return the vector element type once we have support for vectors
-// instead of the identity
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/140177
Fix for elementTypeIfVector
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFon
AmrDeveloper wrote:
I will quickly merge it as a fix for the previous elementTypeIfVector PR to
make it buildable
https://github.com/llvm/llvm-project/pull/140177
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/139444
>From 46d3b466df954eee87a5e5e7df5cb03802d468c7 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 10 May 2025 20:37:05 +0200
Subject: [PATCH 1/2] [CIR] Upstream unary operators for VectorType
---
.../
@@ -54,10 +54,12 @@ namespace direct {
namespace {
/// If the given type is a vector type, return the vector's element type.
/// Otherwise return the given type unchanged.
-// TODO(cir): Return the vector element type once we have support for vectors
-// instead of the identity
@@ -400,4 +400,165 @@ void foo9() {
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
// OGCG: %[[SHR:.*]] = ashr <4 x i32> %[[TMP_A]], %[[TMP_B]]
-// OGCG: store <4 x i32> %[[SHR]], ptr %[[SHR_RE
@@ -1076,20 +1074,41 @@ mlir::LogicalResult
CIRToLLVMUnaryOpLowering::matchAndRewrite(
rewriter.replaceOp(op, adaptor.getInput());
return mlir::success();
case cir::UnaryOpKind::Minus: {
- assert(!isVector &&
- "Add vector handling when vector
@@ -57,7 +57,11 @@ namespace {
// TODO(cir): Return the vector element type once we have support for vectors
// instead of the identity type.
mlir::Type elementTypeIfVector(mlir::Type type) {
- assert(!cir::MissingFeatures::vectorType());
+ if (auto vecType = mlir::dyn_cast(t
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/140125
Upstream vector support in the element type if vector as a required change for
upstreaming other Vec Ops
Issue https://github.com/llvm/llvm-project/issues/136487
>From b9f624e508db8349516f909f0c8e9cb85c04
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/140099
>From de3e5aa6af44a082060ad0edc8ba9bf213b0fba5 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Wed, 14 May 2025 22:25:09 +0200
Subject: [PATCH 1/2] [CIR][LLVMLowering] Upstream binary operators for
Vecto
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/140125
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,s
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 2a56a5d8db006bd466db00989806d548ce042b37 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 22 May 2025 19:38:08 +0200
Subject: [PATCH 1/2] [CIR] Allow use different Int types together in Vec Shif
@@ -1427,12 +1427,12 @@ OpFoldResult cir::SelectOp::fold(FoldAdaptor adaptor) {
//===--===//
LogicalResult cir::ShiftOp::verify() {
mlir::Operation *op = getOperation();
- mlir::Type resType = getResult().g
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/14
Update the verification of ShiftOp for Vector to allow performing shift op
between signed and unsigned integers, similar to LLVM IR
Issue https://github.com/llvm/llvm-project/issues/136487
>From 2a56a5d8d
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/123806
>From 38031e9aed519f4fd3b21dff7e79c69a0150efd9 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Tue, 21 Jan 2025 20:11:21 +0100
Subject: [PATCH] [Clang] Improve testing of non std functions with name
infi
@@ -1427,13 +1427,13 @@ OpFoldResult cir::SelectOp::fold(FoldAdaptor adaptor) {
//===--===//
LogicalResult cir::ShiftOp::verify() {
mlir::Operation *op = getOperation();
- mlir::Type resType = getResult().g
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 2a56a5d8db006bd466db00989806d548ce042b37 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 22 May 2025 19:38:08 +0200
Subject: [PATCH 1/3] [CIR] Allow use different Int types together in Vec Shif
@@ -1427,13 +1427,13 @@ OpFoldResult cir::SelectOp::fold(FoldAdaptor adaptor) {
//===--===//
LogicalResult cir::ShiftOp::verify() {
mlir::Operation *op = getOperation();
- mlir::Type resType = getResult().g
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/140597
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https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/140783
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https://github.com/llvm/llvm-project/pull/140774
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 875db6ee30e8075be50914f62a508511157e8a6f Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 22 May 2025 19:38:08 +0200
Subject: [PATCH 1/4] [CIR] Allow use different Int types together in Vec Shif
@@ -1579,6 +1579,38 @@ OpFoldResult cir::VecExtractOp::fold(FoldAdaptor
adaptor) {
// VecShuffleDynamicOp
//===--===//
+OpFoldResult cir::VecShuffleDynamicOp::fold(FoldAdaptor adaptor) {
+ mlir::Attribute v
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/142393
This change adds support for the Ternary op for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
>From 120e9a69f16545b67c98a0e881183e989ceb9a1e Mon Sep 17 00:00:00 2001
From: AmrDevelope
AmrDeveloper wrote:
- `IntegerVector:$cond` will replaced by `CIR_VectorOfIntType` after merging
https://github.com/llvm/llvm-project/pull/14/
- there will be a follow up PR for the folder
https://github.com/llvm/llvm-project/pull/142393
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/142012
This change adds support for ConvertVectorExpr to convert between vector types
with the same size
Issue https://github.com/llvm/llvm-project/issues/136487
>From 26d9155cc2558d938188627c8afa3260196b7e51 Mo
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/139827
>From 1aa17bae7316805f4becb6d9671dffa8dc1d1e7a Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Tue, 13 May 2025 21:35:06 +0200
Subject: [PATCH 1/2] [CIR] Upstream splat op for VectorType
---
clang/inclu
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141411
>From 8e662a8ccbde1fce77399af5e7b0c24249c1bd96 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sun, 25 May 2025 17:21:34 +0200
Subject: [PATCH 1/4] [CIR] Upstream ShuffleDynamicOp for VectorType
---
cla
https://github.com/AmrDeveloper approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/142218
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 77d3586fede008cf24e25d7bf30c73049de893b8 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 01:47:16 +0200
Subject: [PATCH 1/2] [CIR][NFC] Upstream VectorType support in helper functio
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 77d3586fede008cf24e25d7bf30c73049de893b8 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 01:47:16 +0200
Subject: [PATCH 1/2] [CIR][NFC] Upstream VectorType support in helper functio
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 0e67bfe468c5f543b19de7c02473dc01626d777c Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/8] [CIR] Upstream global initialization for ComplexType
--
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/142288
This change adds support for the Shuffle op for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
>From 1080f1cb13950b3fbeb1536227ee61e2ade9eac7 Mon Sep 17 00:00:00 2001
From: AmrDevelope
AmrDeveloper wrote:
Notes:
- The folder will be in the follow-up PR.
- As far as I understand, they must be the same size, and I think this part of
the Op description in the incubator is not fully correct. Is that correct?
`The size of the result vector does not have to match the size of the
AmrDeveloper wrote:
@xlauko I moved the argument Constraints to use ` TypedArrayAttrBase` and removed the check for indices from the
verifier, not sure if there is a better way to do that, if not I will update it
in the incubator too :D.
https://github.com/llvm/llvm-project/blob/1080f1cb13950b
@@ -1597,9 +1598,9 @@ OpFoldResult cir::VecShuffleDynamicOp::fold(FoldAdaptor
adaptor) {
elements.reserve(numElements);
const uint64_t maskBits = llvm::NextPowerOf2(numElements - 1) - 1;
-for (uint64_t i = 0; i < numElements; i++) {
- cir::IntAttr idxAttr = m
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142315
>From 12c9d3f76360c28efc8ba07ac959af6cf45a6f10 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sun, 1 Jun 2025 19:07:56 +0200
Subject: [PATCH 1/3] [CIR] Implement folder for VecShuffleDynamicOp
---
clan
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142315
>From a2eaa7f28e912f6aa0df909995ec2daf665fbf4d Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sun, 1 Jun 2025 19:07:56 +0200
Subject: [PATCH 1/2] [CIR] Implement folder for VecShuffleDynamicOp
---
clan
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142393
>From 030af8ea55d123d4b32d6a935c6288ea76973897 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Mon, 2 Jun 2025 15:11:17 +0200
Subject: [PATCH 1/3] [CIR] Upstream TernaryOp for VectorType
---
clang/inclu
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/142473
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/142473
We already have constraints in CIROps to make sure that the operands and result
type are vectors
[VecCmpOp](https://github.com/llvm/llvm-project/blob/b88dfb0b23d0a1863414fb9450ee444766bfe7c9/clang/include/
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/14
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@@ -1579,6 +1579,38 @@ OpFoldResult cir::VecExtractOp::fold(FoldAdaptor
adaptor) {
// VecShuffleDynamicOp
//===--===//
+OpFoldResult cir::VecShuffleDynamicOp::fold(FoldAdaptor adaptor) {
+ mlir::Attribute v
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142393
>From 030af8ea55d123d4b32d6a935c6288ea76973897 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Mon, 2 Jun 2025 15:11:17 +0200
Subject: [PATCH 1/2] [CIR] Upstream TernaryOp for VectorType
---
clang/inclu
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 77d3586fede008cf24e25d7bf30c73049de893b8 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 01:47:16 +0200
Subject: [PATCH] [CIR][NFC] Upstream VectorType support in helper function
-
@@ -2156,6 +2156,50 @@ def VecCmpOp : CIR_Op<"vec.cmp", [Pure,
SameTypeOperands]> {
}];
}
+//===--===//
+// VecShuffleOp
+//===--===//
+
+
AmrDeveloper wrote:
> Quoiting the docs: the result of `__builtin_shufflevector` is a vector with
> the same element type as `vec1` and `vec2` but that has an element count
> equal to the number of indices specified.
Thank you, i will put it back to the description
https://github.com/llvm/llv
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142288
>From 1080f1cb13950b3fbeb1536227ee61e2ade9eac7 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 19:53:56 +0200
Subject: [PATCH 1/2] [CIR] Upstream ShuffleOp for VectorType
---
clang/incl
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/142315
This change adds a folder for the VecShuffleDynamicOp
Issue https://github.com/llvm/llvm-project/issues/136487
>From a2eaa7f28e912f6aa0df909995ec2daf665fbf4d Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Da
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142288
>From 1080f1cb13950b3fbeb1536227ee61e2ade9eac7 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 19:53:56 +0200
Subject: [PATCH 1/3] [CIR] Upstream ShuffleOp for VectorType
---
clang/incl
https://github.com/AmrDeveloper edited
https://github.com/llvm/llvm-project/pull/14
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142288
>From 1080f1cb13950b3fbeb1536227ee61e2ade9eac7 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 19:53:56 +0200
Subject: [PATCH 1/4] [CIR] Upstream ShuffleOp for VectorType
---
clang/incl
@@ -0,0 +1,21 @@
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apac
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142288
>From 1080f1cb13950b3fbeb1536227ee61e2ade9eac7 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 19:53:56 +0200
Subject: [PATCH 1/5] [CIR] Upstream ShuffleOp for VectorType
---
clang/incl
@@ -0,0 +1,21 @@
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apac
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142288
>From 1080f1cb13950b3fbeb1536227ee61e2ade9eac7 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 19:53:56 +0200
Subject: [PATCH 1/4] [CIR] Upstream ShuffleOp for VectorType
---
clang/incl
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142393
>From 030af8ea55d123d4b32d6a935c6288ea76973897 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Mon, 2 Jun 2025 15:11:17 +0200
Subject: [PATCH 1/4] [CIR] Upstream TernaryOp for VectorType
---
clang/inclu
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/142393
>From b70523301fc1b1c15434682ea2433511b62190c2 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Mon, 2 Jun 2025 15:11:17 +0200
Subject: [PATCH 1/5] [CIR] Upstream TernaryOp for VectorType
---
clang/inclu
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/142591
Fix the warning related to the missing return statement and multiple return
statements
>From 5a47507bc7f091bd6032b455972095cc95ebbccc Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Tue, 3 Jun 2025 14:0
https://github.com/AmrDeveloper edited
https://github.com/llvm/llvm-project/pull/14
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@@ -16,6 +16,7 @@
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/IR/Types.h"
#include "mlir/Interfaces/DataLayoutInterfaces.h"
+#include "clang/CIR/Dialect/IR/CIRTypes.h"
AmrDeveloper wrote:
Yes, I was adding it to the other file, for the test, it was w
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From bc6569aa45233cb3e08fa149cb45ca2f8c6d4ad1 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 31 May 2025 01:47:16 +0200
Subject: [PATCH] [CIR][NFC] Upstream VectorType support in helper function
-
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/139827
>From f43a15892c7f6217be8bb468d4aef15195d8bc74 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Tue, 13 May 2025 21:35:06 +0200
Subject: [PATCH 1/4] [CIR] Upstream splat op for VectorType
---
clang/inclu
AmrDeveloper wrote:
> Since #14 was merged, please mirror additional changes from
> [llvm/clangir#1626](https://github.com/llvm/clangir/pull/1626) before merging.
I mirrored changes related to the Splat op
https://github.com/llvm/llvm-project/pull/139827
___
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/142946
This change adds a folder for the VecTernaryOp
Issue https://github.com/llvm/llvm-project/issues/136487
>From ac8277b48d0affa78f5e5e943e0179c27dd033ec Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From cd8321c18eecd841907969753653548fbe23d76a Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 01/10] [CIR] Upstream global initialization for ComplexType
https://github.com/AmrDeveloper approved this pull request.
https://github.com/llvm/llvm-project/pull/144950
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/144877
Add support for `__builtin_vectorelements`
Issue https://github.com/llvm/llvm-project/issues/136487
>From 3f07685e76c5ae3dda8c257cb3ac5b33e63ab9ea Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 19
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/143771
>From 301cfa7c4325c50185b3b6e2665dab467078d9f4 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Wed, 11 Jun 2025 20:50:26 +0200
Subject: [PATCH] [CIR] Implement folder for VecSplatOp
---
.../CIR/Dialect/
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/144225
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https://github.com/llvm/llvm-project/pull/144138
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/144225
>From d5c7a04815acee8b792e95fcd376fc492bcadb58 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 14 Jun 2025 16:21:20 +0200
Subject: [PATCH 1/4] [CIR] Upstream ComplexType builtin_complex
---
clang/l
@@ -142,7 +142,8 @@ void CIRCanonicalizePass::runOnOperation() {
// Many operations are here to perform a manual `fold` in
// applyOpPatternsGreedily.
if (isa(op))
+VecExtractOp, VecShuffleOp, VecShuffleDynamicOp, VecSplatOp,
+VecTernaryOp>(o
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/144868
This change adds support for the BinAssign op and LValueToRValue for ComplexType
https://github.com/llvm/llvm-project/issues/141365
>From 8fd8deef461d0a818be9b0d4de66b686dc88a9ed Mon Sep 17 00:00:00 2001
F
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/143771
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/145238
- Merge all vector-type invalid tests into one file.
- Update the names of the functions in the invalid test
Issue https://github.com/llvm/llvm-project/issues/136487
>From 02121b86a2ee7cef7e2fddde059e4efc9
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/144868
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/144868
>From 8fd8deef461d0a818be9b0d4de66b686dc88a9ed Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 19 Jun 2025 12:28:29 +0200
Subject: [PATCH 1/2] [CIR] Upstream BinAssign for ComplexType
---
clang/lib
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/145238
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AmrDeveloper wrote:
I updated the error message; previously, the op name was printed twice
`unexpected error: 'cir.complex.real' op cir.complex.real result type does not
match operand type`
Now
`unexpected error: 'cir.complex.real' op : result type does not match operand
type`
https://gith
https://github.com/AmrDeveloper approved this pull request.
https://github.com/llvm/llvm-project/pull/145551
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/144261
>From 4df7f79a0e41b1269e5a8d4800f8ae5e4e96b569 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sun, 15 Jun 2025 14:44:11 +0200
Subject: [PATCH 1/2] [CIR] Upstream __real__ for ComplexType
---
clang/incl
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/145163
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/144223
>From 167ea0dd6d484389ed03ddfa43a0f6c0cf61cf2f Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 14 Jun 2025 15:12:13 +0200
Subject: [PATCH 1/2] [CIR] Upstream ComplexType ImaginaryLiteral
---
clang/
https://github.com/AmrDeveloper approved this pull request.
LGTM, Thanks!
https://github.com/llvm/llvm-project/pull/144519
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@@ -176,3 +176,27 @@ void foo7() {
// OGCG: store float %[[TMP_A]], ptr %[[C_REAL_PTR]], align 4
// OGCG: store float 2.00e+00, ptr %[[C_IMAG_PTR]], align 4
+void foo9(double r, double i) {
+ double _Complex c = __builtin_complex(r, i);
AmrDeveloper wrote
@@ -142,7 +142,8 @@ void CIRCanonicalizePass::runOnOperation() {
// Many operations are here to perform a manual `fold` in
// applyOpPatternsGreedily.
if (isa(op))
+VecExtractOp, VecShuffleOp, VecShuffleDynamicOp, VecSplatOp,
+VecTernaryOp>(o
@@ -49,6 +49,14 @@ RValue CIRGenFunction::emitBuiltinExpr(const GlobalDecl &gd,
unsigned builtinID,
}
}
+ switch (builtinID) {
+ case Builtin::BI__builtin_complex: {
+mlir::Value real = emitScalarExpr(e->getArg(0));
+mlir::Value imag = emitScalarExpr(e->getArg
https://github.com/AmrDeveloper approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/144123
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https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/144223
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@@ -176,3 +176,27 @@ void foo7() {
// OGCG: store float %[[TMP_A]], ptr %[[C_REAL_PTR]], align 4
// OGCG: store float 2.00e+00, ptr %[[C_IMAG_PTR]], align 4
+void foo9(double r, double i) {
+ double _Complex c = __builtin_complex(r, i);
AmrDeveloper wrote
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