================
@@ -1076,20 +1074,41 @@ mlir::LogicalResult
CIRToLLVMUnaryOpLowering::matchAndRewrite(
rewriter.replaceOp(op, adaptor.getInput());
return mlir::success();
case cir::UnaryOpKind::Minus: {
- assert(!isVector &&
- "Add vector handling when vector types are supported");
- mlir::LLVM::ConstantOp zero = rewriter.create<mlir::LLVM::ConstantOp>(
- loc, llvmType, mlir::IntegerAttr::get(llvmType, 0));
+ mlir::Value zero;
+ if (isVector)
+ zero = rewriter.create<mlir::LLVM::ZeroOp>(loc, llvmType);
+ else
+ zero = rewriter.create<mlir::LLVM::ConstantOp>(
+ loc, llvmType, mlir::IntegerAttr::get(llvmType, 0));
rewriter.replaceOpWithNewOp<mlir::LLVM::SubOp>(
op, llvmType, zero, adaptor.getInput(), maybeNSW);
return mlir::success();
}
case cir::UnaryOpKind::Not: {
// bit-wise compliment operator, implemented as an XOR with -1.
- assert(!isVector &&
- "Add vector handling when vector types are supported");
- mlir::LLVM::ConstantOp minusOne =
rewriter.create<mlir::LLVM::ConstantOp>(
- loc, llvmType, mlir::IntegerAttr::get(llvmType, -1));
+ mlir::Value minusOne;
+ if (isVector) {
+ // Creating a vector object with all -1 values is easier said than
+ // done. It requires a series of insertelement ops.
----------------
AmrDeveloper wrote:
I think yes we can, i will try it
https://github.com/llvm/llvm-project/pull/139444
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
