[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/8] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/9] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 01/10] Add the functional identity and feature queries. --- clang/d

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > So in short: what you're trying to prevent is "this was stored in a variable, > then checked later when we are no longer on the device, thus the answer is > different". Not quite, although that is definitely an interesting consideration. What I am trying to address here is t

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > > as a must have, it allows featureful AMDGCN flavoured SPIR-V to be > > produced, where target specific capability is guarded and chosen or > > discarded when finalising compilation for a concrete target. > > I understand the reasoning behind providing such mechanisms to guar

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %cla

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -585,6 +597,23 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Value *Env = EmitScalarExpr(E->getArg(0)); return Builder.CreateCall(F, {Env}); } + case AMDGPU::BI__builtin_amdgcn_processor_is: { +assert(CGM.getTriple().isSPIRV() &&

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -585,6 +597,23 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Value *Env = EmitScalarExpr(E->getArg(0)); return Builder.CreateCall(F, {Env}); } + case AMDGPU::BI__builtin_amdgcn_processor_is: { +assert(CGM.getTriple().isSPIRV() &&

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 01/11] Add the functional identity and feature queries. --- clang/d

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/7] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/8] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > > You could default the warning to an error to make it more visible to the > user. Not certain if that's a bad idea or not though. > Possibly. I had to drop this for a bit so circling around again, so apologies for the late reply. In the meanwhile, @epilk pointed out somethi

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -37,8 +37,8 @@ static const unsigned SPIRDefIsPrivMap[] = { 0, // cuda_device 0, // cuda_constant 0, // cuda_shared -// SYCL address space values for this map are dummy -0, // sycl_global +// Most SYCL address space values for this map are dummy -

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5384,6 +5384,11 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) { LangAS AS; if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS)) return AS; +if (LangOpts.OpenMPIsTargetDevice && getTriple().isSPIRV()) AlexVlx w

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5384,6 +5384,11 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) { LangAS AS; if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS)) return AS; +if (LangOpts.OpenMPIsTargetDevice && getTriple().isSPIRV()) AlexVlx w

[clang] [llvm] [NFC] Fix bot breakage introduced by #134753 (PR #135697)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/135697 This test needs the amdgpu target, and its absence wreaked havoc with some of the bots, therefore we now require it. >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Dat

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/6] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,21 @@ +// Test that the accelerator code selection pass only gets invoked after linking + +// Ensure Pass HipStdParAcceleratorCodeSelectionPass is not invoked in PreLink. +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -mllvm -amdgpu-enable-hipstdpar -flto -emit-llvm-bc

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,11 @@ +// Check that if we are compiling with fgpu-rdc amdgpu-enable-hipstdpar is not +// passed to CC1, to avoid eager, per TU, removal of potentially accessible +// functions. + +// RUN: %clang -### --hipstdpar --offload-arch=gfx906 %s -nogpulib -nogpuinc \ +// RUN:

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,21 @@ +// Test that the accelerator code selection pass only gets invoked after linking + +// Ensure Pass HipStdParAcceleratorCodeSelectionPass is not invoked in PreLink. +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -mllvm -amdgpu-enable-hipstdpar -flto -emit-llvm-bc

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/7] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/7] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/134753 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 01/11] Add the functional identity and feature queries. --- clang/d

[clang] [llvm] [NFC] Fix bot breakage introduced by #134753 (PR #135697)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/135697 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

AlexVlx wrote: > LLVM Buildbot has detected a new failure on builder > `llvm-clang-x86_64-sie-ubuntu-fast` running on `sie-linux-worker` while > building `clang,llvm` at step 6 "test-build-unified-tree-check-all". > > Full details are available at: > https://lab.llvm.org/buildbot/#/builders/1

[clang] [clang][SPIR-V] Addrspace of opencl_global should always be 1 (PR #136753)

https://github.com/AlexVlx approved this pull request. LGTM, thanks! FWIW, perhaps it'd be worthwhile (as a follow-up, not here) to simply make the DefIsGen AS map correct/valid, and replace the dummy bits? https://github.com/llvm/llvm-project/pull/136753 ___

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)

@@ -1217,11 +1217,13 @@ void CGOpenMPRuntimeGPU::emitParallelCall(CodeGenFunction &CGF, CGBuilderTy &Bld = CGF.Builder; llvm::Value *NumThreadsVal = NumThreads; llvm::Function *WFn = WrapperFunctionsMap[OutlinedFn]; +llvm::FunctionCallee RuntimeFn = OMPBuilder.

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)

@@ -1217,11 +1217,13 @@ void CGOpenMPRuntimeGPU::emitParallelCall(CodeGenFunction &CGF, CGBuilderTy &Bld = CGF.Builder; llvm::Value *NumThreadsVal = NumThreads; llvm::Function *WFn = WrapperFunctionsMap[OutlinedFn]; +llvm::FunctionCallee RuntimeFn = OMPBuilder.

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)

AlexVlx wrote: Overall this seems a bit AS cast heavy in the OMP parts, I wonder if we have a chance to figure out if we cannot just emit things in the right ASes from the get-go? This is the path we took when cleaning up some of this stuff in Clang for C/C++, and whilst it was definitely more

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-s

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-s

[clang] [llvm] [HIP][HIPSTDPAR] Re-work allocation interposition for `hipstdpar` (PR #138790)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/138790 The allocation interposition mode had a number of issues, which are primarily addressed in the library component via . However, it is necessary to interpose some add

[clang] [llvm] [HIP][HIPSTDPAR] Re-work allocation interposition for `hipstdpar` (PR #138790)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/138790 >From 865ff3dff1833607f0d546ab0ebd95b98a8ed71b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 7 May 2025 01:25:17 +0100 Subject: [PATCH 1/2] Re-work allocation interposition for `hipstdpar`. --- clang/do

[clang] [llvm] [HIP][HIPSTDPAR] Re-work allocation interposition for `hipstdpar` (PR #138790)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/138790 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx commented: > A side question, is it legal to use the builtin in unstructured control flow, > like here: https://godbolt.org/z/no7Kzv19r ? Note, if the answer is "no", > then enforcing the builtin to initialize something would (probably) > automatically prevent this c

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/134016 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-s

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