================
@@ -585,6 +597,23 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
llvm::Value *Env = EmitScalarExpr(E->getArg(0));
return Builder.CreateCall(F, {Env});
}
+ case AMDGPU::BI__builtin_amdgcn_processor_is: {
+ assert(CGM.getTriple().isSPIRV() &&
----------------
AlexVlx wrote:
I'm not entirely convinced that it's ideal to have multiple ways of generating
"generic" IRs, one of which is mostly ad-hoc and only known to us, hence I'm
not entirely convinced we want to encourage this. Yes, I appreciate that libc
or ROCDL do this, but perhaps it's better to eventually off-ramp these into
AMDGCN SPIR-V. If you two do not mind, I'd consider leaving this as a follow-up
action, rather than doing it now.
https://github.com/llvm/llvm-project/pull/134016
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