[PATCH] D143507: [RISCV][MC] Mark Zawrs extension as non-experimental

asb created this revision. asb added reviewers: reames, craig.topper. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D122215: [WebAssembly] Initial support for reference type externref in clang

asb added a comment. @pmatos and I have tried and failed to reproduce the assert in the stage3 msan build locally (both of us on separate machines, different environments). We've reached out to @vitalybuka via email for any help in reproducing, because we're somewhat stumped at the moment. Re

[PATCH] D122215: [WebAssembly] Initial support for reference type externref in clang

asb added a comment. In D122215#4119038 , @vitalybuka wrote: > In D122215#4118516 , @asb wrote: > >> @pmatos and I have tried and failed to reproduce the assert in the stage3 >> msan build locally (both of us on

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

asb added a comment. Thanks Philip. I started looking at this too, and agree that something like this is a good next step. I've been looking more closely at the GCC behaviour and noticed a couple of things that might be of interest: - `-march=rv64gc` results in`rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

asb added a comment. I've posted RFC: Resolving issues related to extension versioning in RISC-V which discusses some related issues (I think it complements this patch, rather than anything being

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

asb added a comment. LGTM, and the summary of the discussion in the sync-up call matches my understanding. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143953/new/ https://reviews.llvm.org/D143953 ___

[PATCH] D143507: [RISCV][MC] Mark Zawrs extension as non-experimental

This revision was automatically updated to reflect the committed changes. Closed by commit rGd41a73aa94cb: [RISCV][MC] Mark Zawrs extension as non-experimental (authored by asb). Changed prior to commit: https://reviews.llvm.org/D143507?vs=495562&id=498691#toc Repository: rG LLVM Github Mono

[PATCH] D144696: [RISCV][NFC] Package version number information using RISCVExtensionVersion.

asb added a comment. @ym1813382441 thanks for the contribution. In many cases, this kind of incremental and tightly focused patch is a good way to start things. But in this case, there's a few bigger issues. - As has been pointed out, the discussion about supporting multiple ISA versions has b

[PATCH] D145071: [clang][RISCV] Set HasLegalHalfType to true if zfh is enabled

This revision was automatically updated to reflect the committed changes. Closed by commit rG560065b6ecd5: [clang][RISCV] Set HasLegalHalfType to true if zfh is enabled (authored by asb). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to commit: https://rev

[PATCH] D128612: RISC-V big-endian support implementation

asb added a comment. Thanks for this patch Guy. As just discussed in the RISC-V sync-up call, it would be helpful from a review perspective to write down at least a simple plain-text description of the changes to the psABI doc needed to reflect the BE ABI implemented by GCC (and soon LLVM), per

[PATCH] D128612: RISC-V big-endian support implementation

asb added a comment. In D128612#4349259 , @djtodoro wrote: > In D128612#4345912 , @asb wrote: > >> In D128612#4337037 , @djtodoro >> wrote: >> >>> Hi! I am wondering if s

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

asb updated this revision to Diff 523016. asb edited the summary of this revision. asb added a comment. Now updated to reflect v0.6 of the spec and should be ready for final review and merge https://github.com/riscv/riscv-bfloat16/releases/tag/main CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

asb updated this revision to Diff 523017. asb edited the summary of this revision. asb added a comment. Now updated to version 0.6 of the specification (was previously blocked on a new PDF being tagged). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/ https://reviews.llvm.org

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

asb updated this revision to Diff 523018. asb edited the summary of this revision. asb added a comment. Now updated to version 0.6 of the spec (was previously blocked on a new PDF being tagged and uploaded). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147612/new/ https://reviews.llvm

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

asb updated this revision to Diff 523026. asb added a comment. Rebase and ping (also checked there have been no relevant spec changes since this patch was posted). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149248/new/ https://reviews.llvm.org/D149248 Files: clang/test/Preprocess

[PATCH] D150777: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

asb created this revision. asb added reviewers: craig.topper, kito-cheng, realqhc. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01

[PATCH] D150777: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8e8237686346: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled (authored by asb). Repository: rG LLVM Github Monorepo CHANGES SINC

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

This revision was automatically updated to reflect the committed changes. Closed by commit rG35ff5eba1646: [RISCV][MC] Add support for experimental Zfbfmin extension (authored by asb). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147610/new/ https:

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

This revision was automatically updated to reflect the committed changes. Closed by commit rGb18a81966499: [RISCV][MC] Add support for experimental Zvfbfmin extension (authored by asb). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/ https

[PATCH] D147935: [RISCV] Add SiFive extension support

asb accepted this revision. asb added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147935/new/ https://reviews.llvm.org/D147935 ___ cfe-commits mailing list cfe-commits@lists.llvm.org ht

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

asb accepted this revision. asb added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148124/new/ https://reviews.llvm.org/D148124 ___ cfe-commits mailing list cfe-commits@lists.llvm.org h

[PATCH] D148315: [RISCV] Modify arch string parsing order according to latest riscv spec

asb added a comment. @joshua-arch1: I've posted D146815 to fix the canonical ordering and directly committed rGa35e67fc5be654a7efdfa6125343b90f8960a487 to add some test coverage. Reposito

[PATCH] D148634: [RISCV] Bump Zfa version to 0.2 and correct RISCVUsage description

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2a5661c84158: [RISCV] Bump Zfa version to 0.2 and correct RISCVUsage description (authored by asb). Herald added a project: clang. Herald added a sub

[PATCH] D148315: [RISCV] Modify arch string parsing order according to latest riscv spec

asb added a comment. I'm starting to think we should just remove the ordering rules for z/s/x altogether when parsing arch strings I see that gcc 12.2.0 actually requires s and then z: [asb@purge ~]$ riscv64-linux-gnu-gcc -march=rv64imafdc_svinval_zicbom t.c -c [asb@purge ~]$ riscv64-linux-

[PATCH] D148483: [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGcb7dffdc9a83: [RISCV] Zvk (vector crypto) specification update to 0.5.1… (authored by ego, committed by asb). Herald added a project: clang. Herald a

[PATCH] D148483: [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)

asb added a comment. In D148483#4283898 , @ego wrote: > Thanks for the clarification. I went with the additional alignment. I used to > overdo vertical alignment but it was beaten out of me by the Google C++ style > guide and automatic formatters. Yes,

[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. I'd appreciate some riscv32 RUN lines for completeness, but otherwise LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148817/new/ https://reviews.

[PATCH] D148962: [RISCV] Make Zicntr and Zihpm imply Zicsr.

asb accepted this revision. asb added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148962/new/ https://reviews.llvm.org/D148962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org h

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

asb created this revision. asb added reviewers: reames, kito-cheng, craig.topper, jrtc27, joshua-arch1. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, bruce

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

asb updated this revision to Diff 517105. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149246/new/ https://reviews.llvm.org/D149246 Files: clang/docs/ReleaseNotes.rst clang/test/Driver/riscv-arch.c llvm/lib/Support/RISCVISAInfo.cpp llvm/unittests/Support/RISCVISAInfoTest.cpp I

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

asb updated this revision to Diff 517106. asb added a comment. Add missing doc comment update. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149246/new/ https://reviews.llvm.org/D149246 Files: clang/docs/ReleaseNotes.rst clang/test/Driver/riscv-arch.c llvm/lib/Support/RISCVISAInf

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

asb created this revision. asb added reviewers: reames, craig.topper, kito-cheng. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Mart

[PATCH] D148094: [DRAFT][clang][CodeGen] Break up TargetInfo.cpp [6/6]

asb added a comment. +1 on this refactoring being a good idea. The RISC-V changes seem fine to me (haven't done a detailed line by line review). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148094/new/ https://reviews.llvm.org/D148094 __

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

asb added a comment. I just wanted to check on whether this is ready to review? Also, to what degree are these intrinsics standardised and where is the relevant specification for them? Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138810/n

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. In D148066#4294924 , @kito-cheng wrote: >> My concern would be that as we don't gate CSR names on enabling the relevant >> extension, people could start using CSR names and encodings that could >> change, without opting in via -men

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. FWIW, I've reviewed the CSR numbers vs the spec so LGTM from that perspective. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148066/new/ https://reviews.llvm.org/D148066 ___ cfe-comm

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

asb added a comment. In D149314#4302203 , @aaron.ballman wrote: > Is this a potentially breaking change that we need to call out for users to > be aware of? We should mention this in the Clang release notes I think. Repository: rG LLVM Github Monor

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

asb added a comment. In D149314#4302312 , @reames wrote: > In D149314#4302300 , @aaron.ballman > wrote: > >> In D149314#4302266 , @asb wrote: >> >>> In D149314#4302203

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. Just noting for posterity that we discussed this at last week's RISC-V sync-up call and I think the tentative conclusion (there weren't particularly strong views) was that experiments CSRs should really be gated by -menable-experimental-extensions, with the CSR names gated

[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

asb added a comment. Could you please post a separate patch that has a test that will show the codegen change (and demonstrate how it is unchanged when zbb or xtheadbb)? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151867/new/ https://reviews.llv

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. @jacquesguan I'm not sure on the standardisation process or status for these intrinsics. Perhaps @kito-cheng has an idea? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151547/new/ https://reviews.llvm.org/D151547

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

asb added a comment. In D152279#4403940 , @phosek wrote: > We're planning to default to `-msmall-data-limit=0` for Android and Fuchsia > so I'm supportive of this change because it means less complexity and fewer > differences between platforms. > > I t

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

asb added a comment. One of the key things we've been discussing on this at the LLVM call is that we probably want to keep the small data limit for embedded targets. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152279/new/ https://reviews.llvm.or

[PATCH] D152627: [RISCV] Change the immediate argument to Zvk intrinsics/builtins to i8.

asb added a comment. The patch title should indicate "from i8 to i32" or similar? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152627/new/ https://reviews.llvm.org/D152627 ___ cfe-commits mailing list c

[PATCH] D152628: [RISCV] Add __builtin_riscv_zip/unzip for Zbkb to match gcc.

asb added a comment. I'm not super familiar with these builtins so this might be a silly question why are the new builtins added in this patch LiLi (long int) rather than ZiZi (int32_t) like the old `_32` suffixed builtins? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION htt

[PATCH] D152627: [RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. llvm/test/Bitcode is the other place the autoupgrade tests could go, but it looks like it's not used any more frequently for such tests than llvm/test/CodeGen/$tgt/. Repository: rG LLVM Gi

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

asb added a comment. In D152279#4415974 , @MaskRay wrote: > However, RISC-V `-msmall-data-limit=` is probably a case warranting a > difference. > The global pointer relaxation has a very limited value (benchmarked by > multiple parties, including a part

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

asb updated this revision to Diff 531244. asb added a comment. Rebase and ping. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149248/new/ https://reviews.llvm.org/D149248 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

asb added a comment. I just wanted to document the discussion we had in the RISC-V sync call yesterday. There were no objections to treating the vector crypto work like any other experimental extension, per our current policy (I think the main reason people might object is if substantial churn

[PATCH] D40023: [RISCV] Implement ABI lowering

asb updated this revision to Diff 129607. asb marked 9 inline comments as done. asb added a comment. Herald added a subscriber: niosHD. I've addressed all outstanding comments (a number of response are inline). Additionally: Floats in unions are always passed in GPRs (as clarified here

[PATCH] D40023: [RISCV] Implement ABI lowering

asb added inline comments. Comment at: lib/CodeGen/CGCall.cpp:1937 +RetAttrs.addAttribute(llvm::Attribute::ZExt); +} // FALL THROUGH rjmccall wrote: > I feel like a better design would be to record whether to do a sext or a zext > in the ABIArgI

[PATCH] D41999: Refactor handling of signext/zeroext in ABIArgInfo

asb created this revision. asb added a reviewer: rjmccall. Herald added subscribers: cfe-commits, arichardson. As @rjmccall suggested in https://reviews.llvm.org/D40023, we can get rid of ABIInfo::shouldSignExtUnsignedType (used to handle cases like the Mips calling convention where 32-bit integ

[PATCH] D40023: [RISCV] Implement ABI lowering

asb added inline comments. Comment at: lib/CodeGen/CGCall.cpp:1937 +RetAttrs.addAttribute(llvm::Attribute::ZExt); +} // FALL THROUGH rjmccall wrote: > asb wrote: > > rjmccall wrote: > > > I feel like a better design would be to record whether to

[PATCH] D41999: Refactor handling of signext/zeroext in ABIArgInfo

This revision was automatically updated to reflect the committed changes. Closed by commit rC322396: Refactor handling of signext/zeroext in ABIArgInfo (authored by asb, committed by ). Repository: rC Clang https://reviews.llvm.org/D41999 Files: include/clang/CodeGen/CGFunctionInfo.h lib/

[PATCH] D40023: [RISCV] Implement ABI lowering

asb updated this revision to Diff 129683. asb marked 8 inline comments as done. asb added a comment. Rebase after ABIArgInfo signext/zeroext refactoring https://reviews.llvm.org/D41999 / https://reviews.llvm.org/rL322396. We no longer need to modify CGCall.cpp for unsigned 32-bit return values t

[PATCH] D39963: [RISCV] Add initial RISC-V target and driver support

asb added a comment. Hi Petr, thanks for the report. This should be addressed in https://reviews.llvm.org/rL322435. Repository: rC Clang https://reviews.llvm.org/D39963 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.or

[PATCH] D40023: [RISCV] Implement ABI lowering

asb added inline comments. Comment at: lib/CodeGen/TargetInfo.cpp:8913 + } + return getNaturalAlignIndirect(Ty, /*ByVal=*/true); +} efriedma wrote: > asb wrote: > > efriedma wrote: > > > The spec says "Aggregates larger than 2✕XLEN bits are passed by reference

[PATCH] D40023: [RISCV] Implement ABI lowering

This revision was automatically updated to reflect the committed changes. Closed by commit rL322494: [RISCV] Implement RISCV ABI lowering (authored by asb, committed by ). Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.llvm.org/D40023?vs=129683&id=129878#toc

[PATCH] D40023: [RISCV] Implement ABI lowering

asb added a comment. The riscv32-abi and risc64-abi tests are failing (specifically the vararg checks) on the clang-with-thin-lto and modules-slave-2 buildbots: http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/7892 http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-m

[PATCH] D40023: [RISCV] Implement ABI lowering

asb added a comment. Thanks Eli, that saved me some time - fixed in https://reviews.llvm.org/rL322514 (clang-x86_64-linux-selfhost-modules-2 is now green). Comment at: lib/CodeGen/TargetInfo.cpp:8913 + } + return getNaturalAlignIndirect(Ty, /*ByVal=*/true); +} -

[PATCH] D41271: [RISCV] Propagate -mabi and -march values to GNU assembler.

asb added a comment. In https://reviews.llvm.org/D41271#977222, @apazos wrote: > I tested this on windows and I had to add an assembler placeholder > executable, just like it was done with the linker in the RISCV multilib dir > checked under Inputs. > Other observations, are these known issue

[PATCH] D42673: [RISCV] Pick the correct RISCV linker instead of calling riscv-gcc to link

asb added a comment. My main concern with this patch is that the description doesn't really match what it does. The current in-tree code _doesn't_ call gcc to link for the tested configuration (a multilib toolchain), and this is verified with the tests in test/Driver/riscv32-toolchain.c. https:

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

asb added a comment. In D112987#3257899 , @frasercrmck wrote: > If we're bumping it to 1.0, does that mean it's no longer "experimental"? Whether RVV is non-experimental or not is the big open question for 14.0. I've put it on the agenda for today's sy

[PATCH] D118015: [RISCV][NFC] Rename RequiredExtensions to RequiredFeatures.

asb added a comment. Makes sense to me, but I'll defer to someone else working more actively with this part of the codebase for a final LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D118015/new/ https://reviews.llvm.org/D118015 _

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. Herald added a subscriber: pcwang-thead. Thanks for your work on this. The way you've managed to use multiclasses to handle this with the 'ExtInfo' definitions takes a bit of unpicking to follow, but it does a really good job of keeping the instruction definitions largely u

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. Not an issue for this MC-layer patch, but I've created https://github.com/riscv/riscv-zfinx/issues/14 to point out what seems to be an incorrect statement about the status quo on the ABI for 32-bit floating point types on RV64 in the Zfinx spec. Repository: rG LLVM Gith

[PATCH] D120297: [Driver][RISCV] Add missing rv64 test case

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120297/new/ https://reviews.llvm.org/D120297

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In D118333#3329422 , @asb wrote: > Thanks, I've put this on the agenda for the RISC-V LLVM sync call today. I > think this is more attractive than the previ

[PATCH] D117131: [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental

asb created this revision. asb added reviewers: craig.topper, luismarques. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, StephenFan, vkmr, frasercrmck, jdoerfert, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Marti

[PATCH] D117130: [RISCV] Move Zba/Zbb/Zbc/Zbs out of experimental since they have been ratified.

asb added a comment. Doh - looks like we had the same idea at the same time :) D117131 . I've not done a full diff, but one thing I spotted was that the RISCVInstrInfoZb.td header needs updating. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D117131: [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG33d008b169f3: [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be… (authored by asb). Repository: rG LLVM Github Monorepo CHA

[PATCH] D113237: [RISCV] Support I extension version 2.1

asb added a comment. In D113237#3172492 , @achieveartificialintelligence wrote: > In D113237#3124232 , @luismarques > wrote: > >> In D113237#3124188 , @luismarques >> w

[PATCH] D113237: [RISCV] Support I extension version 2.1

asb added a comment. @kito-cheng In D113237#3183969 , @kito-cheng wrote: > Here is a long discussion[1] at 2019, at that moment I think we all agree > -misa-spec is a good solution, > > However it's kind of awkward for this scheme is ISA spec changing

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

asb added a comment. Can I just check the reasoning on the naming? I see that the bitmanip 0.93 spec proposes _{rv,rv32,rv64}_{opname} intrinsics. Does the __builtin__{riscv,riscv32,riscv64}_opname format match what GCC are doing / planning to do here? Precedent for RVV, for other archs, or som

[PATCH] D99108: [RISCV] Add XFAIL riscv32 for known issue with the old pass manager

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99108/new/ https://reviews.llvm.org/D99108 ___ cfe-co

[PATCH] D94403: [RISCV] Implement new architecture extension macros

asb added a comment. @kito-cheng could you please confirm that this patch handles sub-extensions in the same way GCC does. i.e. -march=rv32izbb0p92 defines `__riscv_zbb` but NOT `__riscv_b`? That seems logical to me, as otherwise it would be cumbersome to check if the whole extension is support

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

asb added a comment. I don't think any of the other patches in the stack update the comment at the top of RISCVInstrInfoB.td to say "version 0.92" rather than "version 0.93", and this is probably a reasonable patch to do it in. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D94617: [RISCV] Add Zba feature and move add.uw and slli.uw to it.

asb accepted this revision. asb added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:61 isExperimentalExtension(StringRef Ext) { - if (Ext == "b" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" || + if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Looks good to me - I'm surprised only Arm, AArch64, and X86 implement this! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108624/new/ https://reviews.

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