llvmbot wrote:
@llvm/pr-subscribers-clang-format
Author: Kazu Hirata (kazutakahirata)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/107962.diff
1 Files Affected:
- (modified) clang/lib/Format/ObjCPropertyAttributeOrderFixer.cpp (+1-3)
``diff
diff --git a/
https://github.com/kazutakahirata created
https://github.com/llvm/llvm-project/pull/107963
MacroAnnotations has three std::optional fields.
Functions makeDeprecation, makeRestrictExpansion, and makeFinal
construct an instance of MacroAnnotations with one field initialized
with a non-default val
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Kazu Hirata (kazutakahirata)
Changes
MacroAnnotations has three std::optional fields.
Functions makeDeprecation, makeRestrictExpansion, and makeFinal
construct an instance of MacroAnnotations with one field initialized
with a non-default v
llvmbot wrote:
@llvm/pr-subscribers-mc
@llvm/pr-subscribers-clang-driver
Author: Ganesh (ganeshgit)
Changes
This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
---
Patch is 31.47 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-projec
https://github.com/ganeshgit created
https://github.com/llvm/llvm-project/pull/107964
This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
>From b68bcc1415151bd84b5868aa2c98663069f45469 Mon Sep 17 00:00:00 2001
From: Ganesh Gopalasubramanian
Date: Thu, 29 Aug 2024 08:54:
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 88bd507dc2dd9c235b54d718cf84e4ef80d94bc9
b68bcc1415151bd84b5868aa2c98663069f45469 --e
@@ -1151,6 +1151,25 @@ static const char
*getAMDProcessorTypeAndSubtype(unsigned Family,
break; // "znver4"
}
break; // family 19h
+ case 26:
boomanaiden154 wrote:
Can you bump the equivalent code in `compiler-rt` too?
https://github.com/llvm
@@ -1151,6 +1151,25 @@ static const char
*getAMDProcessorTypeAndSubtype(unsigned Family,
break; // "znver4"
}
break; // family 19h
+ case 26:
ganeshgit wrote:
Will do!
https://github.com/llvm/llvm-project/pull/107964
_
@@ -1151,6 +1151,25 @@ static const char
*getAMDProcessorTypeAndSubtype(unsigned Family,
break; // "znver4"
}
break; // family 19h
+ case 26:
boomanaiden154 wrote:
I posted some patches a while ago to start unifying things so that there's a
s
@@ -1151,6 +1151,25 @@ static const char
*getAMDProcessorTypeAndSubtype(unsigned Family,
break; // "znver4"
}
break; // family 19h
+ case 26:
ganeshgit wrote:
> I posted some patches a while ago to start unifying things so that there's a
> si
@@ -1151,6 +1151,25 @@ static const char
*getAMDProcessorTypeAndSubtype(unsigned Family,
break; // "znver4"
}
break; // family 19h
+ case 26:
boomanaiden154 wrote:
Oh, looks like I missed it. Sorry about that!
There's https://github.com/llvm/
MichelleCDjunaidi wrote:
PR opened.
https://github.com/llvm/llvm-project/pull/106672
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Author: Timm Baeder
Date: 2024-09-10T06:26:46+02:00
New Revision: 3928edecfbd116d56bbe7411365d50bb567380a1
URL:
https://github.com/llvm/llvm-project/commit/3928edecfbd116d56bbe7411365d50bb567380a1
DIFF:
https://github.com/llvm/llvm-project/commit/3928edecfbd116d56bbe7411365d50bb567380a1.diff
L
https://github.com/tbaederr closed
https://github.com/llvm/llvm-project/pull/107951
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https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/107954
>From 1c66d2767ca20f42b6edaae834cc186be7d23712 Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Mon, 9 Sep 2024 19:39:02 -0700
Subject: [PATCH 1/2] [HLSL] Add `[[hlsl::row_access]]` attribute
This PR introduces
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `clang-hip-vega20` running
on `hip-vega20-0` while building `clang` at step 3 "annotate".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/123/builds/5257
Here is the relevant piece of the build log for
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `bolt-aarch64-ubuntu-clang`
running on `bolt-worker-aarch64` while building `clang,compiler-rt` at step 5
"build-clang-bolt".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/128/builds/609
Here is the
https://github.com/mizvekov created
https://github.com/llvm/llvm-project/pull/107972
This fixes a bug in #18291, that was reported in the PR.
Since this is a bug fix for a patch that was never released, no entries are
added to the changelog.
>From 395ddd73b4dd366155a8718c13410b03bf8c6d32 Mon
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Matheus Izvekov (mizvekov)
Changes
This fixes a bug in #18291, that was reported in the PR.
Since this is a bug fix for a patch that was never released, no entries are
added to the changelog.
---
Full diff: https://github.com/llvm/llvm-p
mizvekov wrote:
@alexfh That's a bug in the patch, thanks for reporting.
This patch fixes it: https://github.com/llvm/llvm-project/pull/107972
https://github.com/llvm/llvm-project/pull/100692
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htt
https://github.com/mizvekov edited
https://github.com/llvm/llvm-project/pull/107972
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https://github.com/hekota created
https://github.com/llvm/llvm-project/pull/107973
We should issue a warning whenever a duplicate resource type attribute is
found. Currently we do that only for `resource_class`. This PR fixes that by
checking for duplicate `is_rov` attributes as well.
Also re
llvmbot wrote:
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-hlsl
Author: Helena Kotas (hekota)
Changes
We should issue a warning whenever a duplicate resource type attribute is
found. Currently we do that only for `resource_class`. This PR fixes that by
checking for duplicate `is_rov`
ganeshgit wrote:
> This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
@RKSimon Pl post your comments. I have few subsequent patches for scheduler
enablement, and some tuning patches lined up as well.
https://github.com/llvm/llvm-project/pull/107964
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/102592
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@@ -0,0 +1,297 @@
+/*===- avx10_2_512satcvtdsintrin.h - AVX10_2_512SATCVTDS intrinsics ===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
https://github.com/phoebewang approved this pull request.
LGTM with one nit.
https://github.com/llvm/llvm-project/pull/102592
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https://github.com/HighW4y2H3ll created
https://github.com/llvm/llvm-project/pull/107974
Encountered several testcase failures when running `ninja check-all`. It was
due to the full path name were shown in the error message instead of the binary
name, and therefore causing the check string mis
llvmbot wrote:
@llvm/pr-subscribers-clang-tidy
Author: None (HighW4y2H3ll)
Changes
Encountered several testcase failures when running `ninja check-all`. It was
due to the full path name were shown in the error message instead of the binary
name, and therefore causing the check string mis
llvmbot wrote:
@llvm/pr-subscribers-clang-tools-extra
Author: None (HighW4y2H3ll)
Changes
Encountered several testcase failures when running `ninja check-all`. It was
due to the full path name were shown in the error message instead of the binary
name, and therefore causing the check str
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/107954
>From 1c66d2767ca20f42b6edaae834cc186be7d23712 Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Mon, 9 Sep 2024 19:39:02 -0700
Subject: [PATCH 1/3] [HLSL] Add `[[hlsl::row_access]]` attribute
This PR introduces
https://github.com/hekota ready_for_review
https://github.com/llvm/llvm-project/pull/107954
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llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Helena Kotas (hekota)
Changes
This PR introduces new HLSL resource type attribute `[[hlsl::row_access]]`.
Presence of this attribute on a resource handle means that the resource must be
accessed in 16-byte blocks at-a-time, or four 32-bit
llvmbot wrote:
@llvm/pr-subscribers-clang-modules
Author: Helena Kotas (hekota)
Changes
This PR introduces new HLSL resource type attribute `[[hlsl::row_access]]`.
Presence of this attribute on a resource handle means that the resource must be
accessed in 16-byte blocks at-a-time, or fou
@@ -14873,41 +14854,6 @@ TreeTransform::TransformLambdaExpr(LambdaExpr
*E) {
/*IsInstantiation*/ true);
SavedContext.pop();
- // Recompute the dependency of the lambda so that we can defer the lambda
call
- // construction until after
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/104856
>From 44e814b925a1ad8ac40fe6904542cbade516c065 Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Mon, 19 Aug 2024 13:34:13 -0700
Subject: [PATCH 1/7] [DirectX] Add DirectXTargetCodeGenInfo
Adds TargetCodeGenInfo
@@ -0,0 +1,400 @@
+//===--- InterpreterValuePrinter.cpp - Value printing utils -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
mstorsjo wrote:
> For the Mips backend itself, I would ask the Mips backend code maintainer...
> but we don't have a maintainer for Mips. And we don't have any buildbots. I'm
> really not sure about adding complexity to a backend which is already
> suffering from a lack of anyone that has any
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