FreddyLeaf wrote:
Sorry, I was OOO, thanks for the fix!
https://github.com/llvm/llvm-project/pull/92338
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banach-space wrote:
Should be fixed by https://github.com/llvm/llvm-project/pull/93794
https://github.com/llvm/llvm-project/pull/92338
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RKSimon wrote:
@FreddyLeaf This is corrupting git checkouts on windows - please can you revert
?
https://github.com/llvm/llvm-project/pull/92338
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banach-space wrote:
Hi, thanks for this contribution. Sadly, it messes up my local checkout on
MacOS (which is insensitive when it comes to files names). These files are
problematic:
* "asm-constraint-jR.ll" and "asm-constraint-jr.ll"
Please, could you rename them so that they are not identica
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/13] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
@@ -57999,13 +58020,25 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget.is64Bit()) {
if (VT == MVT::i8 || VT == MVT::i1)
- return std::m
FreddyLeaf wrote:
[e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3)
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
[e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3)
https://github.com/llvm/llvm-project/pull/92338
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@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
FreddyLeaf wrote:
[e752556](https://github.com/llv
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/13] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
FreddyLeaf wrote:
I'll try. If so, we can refine l
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/llvm/llvm-project/pull/92338
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@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
KanRobert wrote:
You can use sth like
```
not llc
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/92338
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@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
KanRobert wrote:
Nits: Rename this file to llvm/test/CodeGen/X86/apx/asm-constraint-jr.ll to
align with existing one
https://github.com/llvm/llvm-project/pull/92338
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KanRobert wrote:
Nits: Rename this file to llvm/test/CodeGen/X86/apx/asm-constraint-jR.ll to
align with existing one
https://github.com/llvm/llvm-project/pull/92338
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@@ -57999,13 +58020,25 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget.is64Bit()) {
if (VT == MVT::i8 || VT == MVT::i1)
- return std::m
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/12] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
FreddyLeaf wrote:
81f58b6, pls review if I understand correctly.
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
81f58b6
https://github.com/llvm/llvm-project/pull/92338
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@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/11] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return
@@ -57660,6 +57668,19 @@ X86TargetLowering::getSingleConstraintMatchWeight(
break;
}
break;
+ case 'j':
+if (StringRef(Constraint).size() != 2)
+ break;
+switch (Constraint[1]) {
+default:
+ return CW_Invalid;
+case 'r':
+case 'R':
+
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
KanRobert wrote:
Merge this into llvm/test/CodeGen/X86/apx/inline-asm-jr-constraint.ll
You can add `not` at each run line. llc does not stop processing when
encountering such kind of error.
https://github.com/llvm/llvm-project/pull/92338
_
KanRobert wrote:
Remove this test and update llvm/test/CodeGen/X86/apx/asm-constraint.ll
https://github.com/llvm/llvm-project/pull/92338
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@@ -57660,6 +57668,19 @@ X86TargetLowering::getSingleConstraintMatchWeight(
break;
}
break;
+ case 'j':
+if (StringRef(Constraint).size() != 2)
+ break;
+switch (Constraint[1]) {
+default:
+ return CW_Invalid;
+case 'r':
+case 'R':
+
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return
@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
--
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/10] [X86] Support EGPR for inline assembly.
"jR": explictly ena
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+switch (Constraint[1]) {
+default:
+ break;
+case 'R':
+ if
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/9] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+switch (Constraint[1]) {
+default:
+ break;
+case 'R':
+ if
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
https://github.com/KanRobert deleted
https://github.com/llvm/llvm-project/pull/92338
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@@ -346,6 +346,9 @@ def FeatureNF : SubtargetFeature<"nf", "HasNF", "true",
"Support status flags update suppression">;
def FeatureCF : SubtargetFeature<"cf", "HasCF", "true",
"Support conditional faulting">;
+de
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
--
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
ping @KanRobert
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/8] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
https://github.com/nickdesaulniers approved this pull request.
someone with more knowledge about EGPR should approve this as well, but I'm
happy with the code style for the additions.
https://github.com/llvm/llvm-project/pull/92338
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@@ -58016,15 +58035,27 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
break;
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
+ if (Subtarget.useInlineAsmGPR32()) {
+if (VT == MVT::i8 || VT == MVT::i1)
+
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/8] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
@@ -58016,15 +58035,27 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
break;
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
+ if (Subtarget.useInlineAsmGPR32()) {
+if (VT == MVT::i8 || VT == MVT::i1)
+
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
--check-prefix=EGPR
+; RUN: llc -mtriple=x86_64
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/7] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
--check-prefix=EGPR
+; RUN: llc -mtriple=x86_64
FreddyLeaf wrote:
> `
> [4087704](/llvm/llvm-project/pull/92338/commits/40877041618aa8f472f0da7cda06c21f4007a1ec)`
Thanks reminding. Added in 4087704, pls help review.
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/6] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
jyknight wrote:
Please update the constraint code list
https://llvm.org/docs/LangRef.html#supported-constraint-code-list with any new
codes.
https://github.com/llvm/llvm-project/pull/92338
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https
FreddyLeaf wrote:
[4d1ad30](https://github.com/llvm/llvm-project/pull/92338/commits/4d1ad3090416cda320c88f1ddc0937b5749e64b4)
moved but not merged. These two constraints will behavior different under
-mattr=+egpr.
https://github.com/llvm/llvm-project/pull/923
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/5] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
KanRobert wrote:
Merge the two tests into one and put it under apx directory.
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
ping for review
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/4] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/92338
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@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> SSELevel reli
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
> > > Will the
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
SSELevel relie
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> > Will the fe
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
> Will the fea
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> `mcmodel` may
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/92338
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@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
Will the featur
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/3] [X86] Support EGPR for inline assembly.
"jR": explictly enabl
FreddyLeaf wrote:
> Please put the corresponding GCC links for your description
done.
https://github.com/llvm/llvm-project/pull/92338
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