[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

asb wrote: My understanding from the sync-up call just now is you're planning to drop lr/sc intrinsics due to the concerns listed in this thread (which I share), but will keep pushing the zawrs intrinsics. https://github.com/llvm/llvm-project/pull/94578

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

efriedma-quic wrote: > I don't know much about there intrinsics on ARM, what are the stronger > guarantees? The Arm specifies that there's a memory reservation, and you can write whatever operations you want as long as you don't break that reservation. And the reservation is usually only a f

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

topperc wrote: > Compilers are free to insert whatever stack spills and reloads they want in > between your inline assembly blocks or intrinsic calls Especially with -O0. https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cf

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

jrtc27 wrote: > If we are talking about the necessariness of adding these intrinsics, please > refer to the ARM implementations in DPDK > (https://github.com/DPDK/dpdk/blob/76cef1af8bdaeaf67a5c4ca5df3f221df994dc46/lib/eal/arm/include/rte_pause_64.h). > > We want to use Zawrs&Zalrsc instruction

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

wangpc-pp wrote: If we are talking about the necessariness of adding these intrinsics, please refer to the ARM implementations in DPDK (https://github.com/DPDK/dpdk/blob/76cef1af8bdaeaf67a5c4ca5df3f221df994dc46/lib/eal/arm/include/rte_pause_64.h).We want to use https://github.com/llvm/llvm-p

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

jrtc27 wrote: > > lr/sc builtins are extremely fragile: there's no reasonable way for the > > compiler to guarantee that the sc is placed in such a way that it will > > eventually succeed. > > I think the user should have enough knowledges about lr/sc to make the logic > reasonable. It's not

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

wangpc-pp wrote: > lr/sc builtins are extremely fragile: there's no reasonable way for the > compiler to guarantee that the sc is placed in such a way that it will > eventually succeed. I think the user should have enough knowledges about lr/sc to make the logic reasonable. If we don't provid

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

efriedma-quic wrote: lr/sc builtins are extremely fragile: there's no reasonable way for the compiler to guarantee that the sc is placed in such a way that it will eventually succeed. (The equivalent intrinsics do exist on ARM, but ARM has significantly stronger guarantees here. Even then, i

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/94578 >From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 6 Jun 2024 13:48:34 +0800 Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?