https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/94578
>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6-beta.1
---
clang/include/clang/Basic/BuiltinsRISCV.td | 18 ++
clang/lib/CodeGen/CGBuiltin.cpp | 22 ++
clang/lib/Headers/CMakeLists.txt | 1 +
clang/lib/Headers/riscv_atomics.h | 36 +++
clang/lib/Sema/SemaRISCV.cpp | 10 +-
.../RISCV/atomics-intrinsics/zalrsc-error.c | 13 +
.../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++++++++++++++++++
.../CodeGen/RISCV/atomics-intrinsics/zawrs.c | 42 ++++
llvm/include/llvm/IR/IntrinsicsRISCV.td | 32 +++
llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 25 ++
llvm/lib/Target/RISCV/RISCVInstrInfoZa.td | 5 +-
llvm/test/CodeGen/RISCV/zalrsc-rv32.ll | 74 ++++++
llvm/test/CodeGen/RISCV/zalrsc-rv64.ll | 74 ++++++
llvm/test/CodeGen/RISCV/zawrs.ll | 33 +++
14 files changed, 605 insertions(+), 2 deletions(-)
create mode 100644 clang/lib/Headers/riscv_atomics.h
create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes =
[CustomTypeChecking] in {
def ntl_load : RISCVBuiltin<"void(...)">;
def ntl_store : RISCVBuiltin<"void(...)">;
} // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===----------------------------------------------------------------------===//
+// Zawrs extension.
+//===----------------------------------------------------------------------===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===----------------------------------------------------------------------===//
+// Zalrsc extension.
+//===----------------------------------------------------------------------===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
ID = Intrinsic::riscv_sm3p1;
break;
+ // Zawrs
+ case RISCV::BI__builtin_riscv_wrs_nto:
+ ID = Intrinsic::riscv_wrs_nto;
+ break;
+ case RISCV::BI__builtin_riscv_wrs_sto:
+ ID = Intrinsic::riscv_wrs_sto;
+ break;
+
+ // Zalrsc
+ case RISCV::BI__builtin_riscv_lr_w:
+ ID = Intrinsic::riscv_lr_w;
+ break;
+ case RISCV::BI__builtin_riscv_lr_d:
+ ID = Intrinsic::riscv_lr_d;
+ break;
+ case RISCV::BI__builtin_riscv_sc_w:
+ ID = Intrinsic::riscv_sc_w;
+ break;
+ case RISCV::BI__builtin_riscv_sc_d:
+ ID = Intrinsic::riscv_sc_d;
+ break;
+
// Zihintntl
case RISCV::BI__builtin_riscv_ntl_load: {
llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
)
set(riscv_files
+ riscv_atomics.h
riscv_bitmanip.h
riscv_crypto.h
riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0000000000000..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*===---- riscv_atomics.h - RISC-V atomics intrinsics ----------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __RISCV_ATOMICS_H
+#define __RISCV_ATOMICS_H
+
+#ifdef __riscv_zalrsc
+enum {
+ __RISCV_ORDER_NONE = 0,
+ __RISCV_ORDER_AQ = 1,
+ __RISCV_ORDER_RL = 2,
+ __RISCV_ORDER_AQ_RL = 3
+};
+
+#define __riscv_lr_w __builtin_riscv_lr_w
+#define __riscv_sc_w __builtin_riscv_sc_w
+
+#if __riscv_xlen == 64
+#define __riscv_lr_d __builtin_riscv_lr_d
+#define __riscv_sc_d __builtin_riscv_sc_d
+#endif
+
+#endif
+
+#ifdef __riscv_zawrs
+#define __riscv_wrs_nto __builtin_riscv_wrs_nto
+#define __riscv_wrs_sto __builtin_riscv_wrs_sto
+#endif
+
+#endif
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index fd4fc15c1fd79..0b69b72cea8bb 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -1303,7 +1303,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:
return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 4);
case RISCV::BI__builtin_riscv_ntl_load:
- case RISCV::BI__builtin_riscv_ntl_store:
+ case RISCV::BI__builtin_riscv_ntl_store: {
DeclRefExpr *DRE =
cast<DeclRefExpr>(TheCall->getCallee()->IgnoreParenCasts());
assert((BuiltinID == RISCV::BI__builtin_riscv_ntl_store ||
@@ -1368,6 +1368,14 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const
TargetInfo &TI,
return false;
}
+ case RISCV::BI__builtin_riscv_lr_w:
+ case RISCV::BI__builtin_riscv_lr_d:
+ return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 3);
+ case RISCV::BI__builtin_riscv_sc_w:
+ case RISCV::BI__builtin_riscv_sc_d:
+ return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 3);
+ }
+
return false;
}
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
b/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
new file mode 100644
index 0000000000000..d274077c9acfd
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
@@ -0,0 +1,13 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zalrsc -S -verify %s -o -
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zalrsc -S -verify %s -o -
+
+#include <riscv_atomics.h>
+
+int zalrsc_lr_w(int* ptr) {
+ return __riscv_lr_w(ptr, 4); // expected-error {{argument value 4 is outside
the valid range [0, 3]}}
+}
+
+int zalrsc_sc_w(int v, int* ptr) {
+ return __riscv_sc_w(v, ptr, 4); // expected-error {{argument value 4 is
outside the valid range [0, 3]}}
+}
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
b/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
new file mode 100644
index 0000000000000..662ac53ee1e57
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
@@ -0,0 +1,222 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zalrsc -disable-O0-optnone
\
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefixes=CHECK-RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zalrsc -disable-O0-optnone
\
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <stdint.h>
+#include <riscv_atomics.h>
+
+// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_lr_w_none
+// CHECK-RV32-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.lr.w(ptr [[PTR]],
i32 0)
+// CHECK-RV32-NEXT: ret i32 [[TMP0]]
+//
+// CHECK-RV64-LABEL: define dso_local signext i32 @zalrsc_lr_w_none
+// CHECK-RV64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.lr.w(ptr [[PTR]],
i32 0)
+// CHECK-RV64-NEXT: ret i32 [[TMP0]]
+//
+int zalrsc_lr_w_none(int* ptr) {
+ return __riscv_lr_w(ptr, __RISCV_ORDER_NONE);
+}
+
+// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_lr_w_aq
+// CHECK-RV32-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.lr.w(ptr [[PTR]],
i32 1)
+// CHECK-RV32-NEXT: ret i32 [[TMP0]]
+//
+// CHECK-RV64-LABEL: define dso_local signext i32 @zalrsc_lr_w_aq
+// CHECK-RV64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.lr.w(ptr [[PTR]],
i32 1)
+// CHECK-RV64-NEXT: ret i32 [[TMP0]]
+//
+int zalrsc_lr_w_aq(int* ptr) {
+ return __riscv_lr_w(ptr, __RISCV_ORDER_AQ);
+}
+
+// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_lr_w_rl
+// CHECK-RV32-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.lr.w(ptr [[PTR]],
i32 2)
+// CHECK-RV32-NEXT: ret i32 [[TMP0]]
+//
+// CHECK-RV64-LABEL: define dso_local signext i32 @zalrsc_lr_w_rl
+// CHECK-RV64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.lr.w(ptr [[PTR]],
i32 2)
+// CHECK-RV64-NEXT: ret i32 [[TMP0]]
+//
+int zalrsc_lr_w_rl(int* ptr) {
+ return __riscv_lr_w(ptr, __RISCV_ORDER_RL);
+}
+
+// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_lr_w_aqrl
+// CHECK-RV32-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.lr.w(ptr [[PTR]],
i32 3)
+// CHECK-RV32-NEXT: ret i32 [[TMP0]]
+//
+// CHECK-RV64-LABEL: define dso_local signext i32 @zalrsc_lr_w_aqrl
+// CHECK-RV64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.lr.w(ptr [[PTR]],
i32 3)
+// CHECK-RV64-NEXT: ret i32 [[TMP0]]
+//
+int zalrsc_lr_w_aqrl(int* ptr) {
+ return __riscv_lr_w(ptr, __RISCV_ORDER_AQ_RL);
+}
+
+// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_sc_w_none
+// CHECK-RV32-SAME: (i32 noundef [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sc.w(i32 [[V]], ptr
[[PTR]], i32 0)
+// CHECK-RV32-NEXT: ret i32 [[TMP0]]
+//
+// CHECK-RV64-LABEL: define dso_local signext i32 @zalrsc_sc_w_none
+// CHECK-RV64-SAME: (i32 noundef signext [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sc.w(i32 [[V]], ptr
[[PTR]], i32 0)
+// CHECK-RV64-NEXT: ret i32 [[TMP0]]
+//
+int zalrsc_sc_w_none(int v, int* ptr) {
+ return __riscv_sc_w(v, ptr, __RISCV_ORDER_NONE);
+}
+
+// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_sc_w_aq
+// CHECK-RV32-SAME: (i32 noundef [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sc.w(i32 [[V]], ptr
[[PTR]], i32 1)
+// CHECK-RV32-NEXT: ret i32 [[TMP0]]
+//
+// CHECK-RV64-LABEL: define dso_local signext i32 @zalrsc_sc_w_aq
+// CHECK-RV64-SAME: (i32 noundef signext [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sc.w(i32 [[V]], ptr
[[PTR]], i32 1)
+// CHECK-RV64-NEXT: ret i32 [[TMP0]]
+//
+int zalrsc_sc_w_aq(int v, int* ptr) {
+ return __riscv_sc_w(v, ptr, __RISCV_ORDER_AQ);
+}
+
+// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_sc_w_rl
+// CHECK-RV32-SAME: (i32 noundef [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sc.w(i32 [[V]], ptr
[[PTR]], i32 2)
+// CHECK-RV32-NEXT: ret i32 [[TMP0]]
+//
+// CHECK-RV64-LABEL: define dso_local signext i32 @zalrsc_sc_w_rl
+// CHECK-RV64-SAME: (i32 noundef signext [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sc.w(i32 [[V]], ptr
[[PTR]], i32 2)
+// CHECK-RV64-NEXT: ret i32 [[TMP0]]
+//
+int zalrsc_sc_w_rl(int v, int* ptr) {
+ return __riscv_sc_w(v, ptr, __RISCV_ORDER_RL);
+}
+
+// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_sc_w_aqrl
+// CHECK-RV32-SAME: (i32 noundef [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sc.w(i32 [[V]], ptr
[[PTR]], i32 3)
+// CHECK-RV32-NEXT: ret i32 [[TMP0]]
+//
+// CHECK-RV64-LABEL: define dso_local signext i32 @zalrsc_sc_w_aqrl
+// CHECK-RV64-SAME: (i32 noundef signext [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sc.w(i32 [[V]], ptr
[[PTR]], i32 3)
+// CHECK-RV64-NEXT: ret i32 [[TMP0]]
+//
+int zalrsc_sc_w_aqrl(int v, int* ptr) {
+ return __riscv_sc_w(v, ptr, __RISCV_ORDER_AQ_RL);
+}
+
+#if __riscv_xlen == 64
+// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_lr_d_none
+// CHECK-RV64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.lr.d(ptr [[PTR]],
i32 0)
+// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+//
+int64_t zalrsc_lr_d_none(int64_t* ptr) {
+ return __riscv_lr_d(ptr, __RISCV_ORDER_NONE);
+}
+
+// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_lr_d_aq
+// CHECK-RV64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.lr.d(ptr [[PTR]],
i32 1)
+// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+//
+int64_t zalrsc_lr_d_aq(int64_t* ptr) {
+ return __riscv_lr_d(ptr, __RISCV_ORDER_AQ);
+}
+
+// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_lr_d_rl
+// CHECK-RV64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.lr.d(ptr [[PTR]],
i32 2)
+// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+//
+int64_t zalrsc_lr_d_rl(int64_t* ptr) {
+ return __riscv_lr_d(ptr, __RISCV_ORDER_RL);
+}
+
+// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_lr_d_aqrl
+// CHECK-RV64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.lr.d(ptr [[PTR]],
i32 3)
+// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+//
+int64_t zalrsc_lr_d_aqrl(int64_t* ptr) {
+ return __riscv_lr_d(ptr, __RISCV_ORDER_AQ_RL);
+}
+
+// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_sc_d_none
+// CHECK-RV64-SAME: (i64 noundef [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sc.d(i64 [[V]], ptr
[[PTR]], i32 0)
+// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+//
+int64_t zalrsc_sc_d_none(int64_t v, int64_t* ptr) {
+ return __riscv_sc_d(v, ptr, __RISCV_ORDER_NONE);
+}
+
+// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_sc_d_aq
+// CHECK-RV64-SAME: (i64 noundef [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sc.d(i64 [[V]], ptr
[[PTR]], i32 1)
+// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+//
+int64_t zalrsc_sc_d_aq(int64_t v, int64_t* ptr) {
+ return __riscv_sc_d(v, ptr, __RISCV_ORDER_AQ);
+}
+
+// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_sc_d_rl
+// CHECK-RV64-SAME: (i64 noundef [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sc.d(i64 [[V]], ptr
[[PTR]], i32 2)
+// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+//
+int64_t zalrsc_sc_d_rl(int64_t v, int64_t* ptr) {
+ return __riscv_sc_d(v, ptr, __RISCV_ORDER_RL);
+}
+
+// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_sc_d_aqrl
+// CHECK-RV64-SAME: (i64 noundef [[V:%.*]], ptr noundef [[PTR:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sc.d(i64 [[V]], ptr
[[PTR]], i32 3)
+// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+//
+int64_t zalrsc_sc_d_aqrl(int64_t v, int64_t* ptr) {
+ return __riscv_sc_d(v, ptr, __RISCV_ORDER_AQ_RL);
+}
+
+#endif
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
new file mode 100644
index 0000000000000..998655e67a160
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zawrs -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefixes=CHECK-RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zawrs -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_atomics.h>
+
+// CHECK-RV32-LABEL: define dso_local void @zawrs_nto
+// CHECK-RV32-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: call void @llvm.riscv.wrs.nto()
+// CHECK-RV32-NEXT: ret void
+//
+// CHECK-RV64-LABEL: define dso_local void @zawrs_nto
+// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: call void @llvm.riscv.wrs.nto()
+// CHECK-RV64-NEXT: ret void
+//
+void zawrs_nto(){
+ __riscv_wrs_nto();
+}
+
+// CHECK-RV32-LABEL: define dso_local void @zawrs_sto
+// CHECK-RV32-SAME: () #[[ATTR0]] {
+// CHECK-RV32-NEXT: entry:
+// CHECK-RV32-NEXT: call void @llvm.riscv.wrs.sto()
+// CHECK-RV32-NEXT: ret void
+//
+// CHECK-RV64-LABEL: define dso_local void @zawrs_sto
+// CHECK-RV64-SAME: () #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: call void @llvm.riscv.wrs.sto()
+// CHECK-RV64-NEXT: ret void
+//
+void zawrs_sto(){
+ __riscv_wrs_sto();
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td
b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 4c4e7351212f8..c9a0e75645694 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -124,6 +124,38 @@ let TargetPrefix = "riscv" in {
[IntrNoMem, IntrSpeculatable,
ImmArg<ArgIndex<2>>]>;
} // TargetPrefix = "riscv"
+//===----------------------------------------------------------------------===//
+// 'Zawrs' (Wait on Reservation Set)
+
+let TargetPrefix = "riscv" in {
+ def int_riscv_wrs_nto
+ : DefaultAttrsIntrinsic<[], [], [IntrHasSideEffects]>;
+ def int_riscv_wrs_sto
+ : DefaultAttrsIntrinsic<[], [], [IntrHasSideEffects]>;
+} // TargetPrefix = "riscv"
+
+//===----------------------------------------------------------------------===//
+// 'Zalrsc' (Load-Reserved/Store-Conditional)
+
+let TargetPrefix = "riscv" in {
+ def int_riscv_lr_w
+ : DefaultAttrsIntrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadMem, ImmArg<ArgIndex<1>>]>;
+ def int_riscv_lr_d
+ : DefaultAttrsIntrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadMem, ImmArg<ArgIndex<1>>]>;
+ def int_riscv_sc_w
+ : DefaultAttrsIntrinsic<[llvm_i32_ty],
+ [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrWriteMem, ImmArg<ArgIndex<2>>]>;
+ def int_riscv_sc_d
+ : DefaultAttrsIntrinsic<[llvm_i64_ty],
+ [llvm_i64_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrWriteMem, ImmArg<ArgIndex<2>>]>;
+} // TargetPrefix = "riscv"
+
//===----------------------------------------------------------------------===//
// Vectors
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 814e0ddf111e6..5dbf954995bed 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -136,6 +136,31 @@ let Predicates = [HasAtomicLdSt, IsRV64] in {
def : StPat<atomic_store_64, SD, GPR, i64>;
}
+/// LR/SC intrinsics patterns
+multiclass LRPat<Intrinsic intrinsic, string inst> {
+ def : Pat<(intrinsic GPR:$src, 0), (!cast<Instruction>(inst) GPR:$src)>;
+ def : Pat<(intrinsic GPR:$src, 1), (!cast<Instruction>(inst # "_AQ")
GPR:$src)>;
+ def : Pat<(intrinsic GPR:$src, 2), (!cast<Instruction>(inst # "_RL")
GPR:$src)>;
+ def : Pat<(intrinsic GPR:$src, 3), (!cast<Instruction>(inst # "_AQ_RL")
GPR:$src)>;
+}
+
+multiclass SCPat<Intrinsic intrinsic, string inst> {
+ def : Pat<(intrinsic GPR:$src, GPR:$dst, 0), (!cast<Instruction>(inst)
GPR:$src, GPR:$dst)>;
+ def : Pat<(intrinsic GPR:$src, GPR:$dst, 1), (!cast<Instruction>(inst #
"_AQ") GPR:$src, GPR:$dst)>;
+ def : Pat<(intrinsic GPR:$src, GPR:$dst, 2), (!cast<Instruction>(inst #
"_RL") GPR:$src, GPR:$dst)>;
+ def : Pat<(intrinsic GPR:$src, GPR:$dst, 3), (!cast<Instruction>(inst #
"_AQ_RL") GPR:$src, GPR:$dst)>;
+}
+
+let Predicates = [HasStdExtAOrZalrsc] in {
+ defm : LRPat<int_riscv_lr_w, "LR_W">;
+ defm : SCPat<int_riscv_sc_w, "SC_W">;
+} // Predicates = [HasStdExtAOrZalrsc]
+
+let Predicates = [HasStdExtAOrZalrsc, IsRV64] in {
+ defm : LRPat<int_riscv_lr_d, "LR_D">;
+ defm : SCPat<int_riscv_sc_d, "SC_D">;
+} // Predicates = [HasStdExtAOrZalrsc, IsRV64]
+
/// AMOs
multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
index 0cd41cac218f9..54beda20dbad5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
@@ -123,7 +123,7 @@ defm : AMOCASPat<"atomic_cmp_swap_64", "AMOCAS_D_RV64",
i64, [IsRV64]>;
// Zawrs (Wait-on-Reservation-Set)
//===----------------------------------------------------------------------===//
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
class WRSInst<bits<12> funct12, string opcodestr>
: RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, ""> {
let rs1 = 0;
@@ -134,6 +134,9 @@ class WRSInst<bits<12> funct12, string opcodestr>
let Predicates = [HasStdExtZawrs] in {
def WRS_NTO : WRSInst<0b000000001101, "wrs.nto">, Sched<[]>;
def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>;
+
+def : Pat<(int_riscv_wrs_nto), (WRS_NTO)>;
+def : Pat<(int_riscv_wrs_sto), (WRS_NTO)>;
} // Predicates = [HasStdExtZawrs]
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
b/llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
new file mode 100644
index 0000000000000..f71836fb553aa
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s |
FileCheck %s
+
+define i32 @lr_w_none(ptr %src) {
+; CHECK-LABEL: lr_w_none:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lr.w a0, (a0)
+; CHECK-NEXT: ret
+ %ret = call i32 @llvm.riscv.lr.w(ptr %src, i32 0)
+ ret i32 %ret
+}
+
+define i32 @lr_w_aq(ptr %src) {
+; CHECK-LABEL: lr_w_aq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lr.w.aq a0, (a0)
+; CHECK-NEXT: ret
+ %ret = call i32 @llvm.riscv.lr.w(ptr %src, i32 1)
+ ret i32 %ret
+}
+
+define i32 @lr_w_rl(ptr %src) {
+; CHECK-LABEL: lr_w_rl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lr.w.rl a0, (a0)
+; CHECK-NEXT: ret
+ %ret = call i32 @llvm.riscv.lr.w(ptr %src, i32 2)
+ ret i32 %ret
+}
+
+define i32 @lr_w_aq_rl(ptr %src) {
+; CHECK-LABEL: lr_w_aq_rl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lr.w.aqrl a0, (a0)
+; CHECK-NEXT: ret
+ %ret = call i32 @llvm.riscv.lr.w(ptr %src, i32 3)
+ ret i32 %ret
+}
+
+define i32 @sc_w_none(i32 %v, ptr %src) {
+; CHECK-LABEL: sc_w_none:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sc.w a0, a1, (a0)
+; CHECK-NEXT: ret
+ %ret = call i32 @llvm.riscv.sc.w(i32 %v, ptr %src, i32 0)
+ ret i32 %ret
+}
+
+define i32 @sc_w_aq(i32 %v, ptr %src) {
+; CHECK-LABEL: sc_w_aq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sc.w.aq a0, a1, (a0)
+; CHECK-NEXT: ret
+ %ret = call i32 @llvm.riscv.sc.w(i32 %v, ptr %src, i32 1)
+ ret i32 %ret
+}
+
+define i32 @sc_w_rl(i32 %v, ptr %src) {
+; CHECK-LABEL: sc_w_rl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sc.w.rl a0, a1, (a0)
+; CHECK-NEXT: ret
+ %ret = call i32 @llvm.riscv.sc.w(i32 %v, ptr %src, i32 2)
+ ret i32 %ret
+}
+
+define i32 @sc_w_aq_rl(i32 %v, ptr %src) {
+; CHECK-LABEL: sc_w_aq_rl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sc.w.aqrl a0, a1, (a0)
+; CHECK-NEXT: ret
+ %ret = call i32 @llvm.riscv.sc.w(i32 %v, ptr %src, i32 3)
+ ret i32 %ret
+}
diff --git a/llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
b/llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
new file mode 100644
index 0000000000000..b08fdc841cc4f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s |
FileCheck %s
+
+define i64 @lr_d_none(ptr %src) {
+; CHECK-LABEL: lr_d_none:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lr.d a0, (a0)
+; CHECK-NEXT: ret
+ %ret = call i64 @llvm.riscv.lr.d(ptr %src, i32 0)
+ ret i64 %ret
+}
+
+define i64 @lr_d_aq(ptr %src) {
+; CHECK-LABEL: lr_d_aq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lr.d.aq a0, (a0)
+; CHECK-NEXT: ret
+ %ret = call i64 @llvm.riscv.lr.d(ptr %src, i32 1)
+ ret i64 %ret
+}
+
+define i64 @lr_d_rl(ptr %src) {
+; CHECK-LABEL: lr_d_rl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lr.d.rl a0, (a0)
+; CHECK-NEXT: ret
+ %ret = call i64 @llvm.riscv.lr.d(ptr %src, i32 2)
+ ret i64 %ret
+}
+
+define i64 @lr_d_aq_rl(ptr %src) {
+; CHECK-LABEL: lr_d_aq_rl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lr.d.aqrl a0, (a0)
+; CHECK-NEXT: ret
+ %ret = call i64 @llvm.riscv.lr.d(ptr %src, i32 3)
+ ret i64 %ret
+}
+
+define i64 @sc_d_none(i64 %v, ptr %src) {
+; CHECK-LABEL: sc_d_none:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sc.d a0, a1, (a0)
+; CHECK-NEXT: ret
+ %ret = call i64 @llvm.riscv.sc.d(i64 %v, ptr %src, i32 0)
+ ret i64 %ret
+}
+
+define i64 @sc_d_aq(i64 %v, ptr %src) {
+; CHECK-LABEL: sc_d_aq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sc.d.aq a0, a1, (a0)
+; CHECK-NEXT: ret
+ %ret = call i64 @llvm.riscv.sc.d(i64 %v, ptr %src, i32 1)
+ ret i64 %ret
+}
+
+define i64 @sc_d_rl(i64 %v, ptr %src) {
+; CHECK-LABEL: sc_d_rl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sc.d.rl a0, a1, (a0)
+; CHECK-NEXT: ret
+ %ret = call i64 @llvm.riscv.sc.d(i64 %v, ptr %src, i32 2)
+ ret i64 %ret
+}
+
+define i64 @sc_d_aq_rl(i64 %v, ptr %src) {
+; CHECK-LABEL: sc_d_aq_rl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sc.d.aqrl a0, a1, (a0)
+; CHECK-NEXT: ret
+ %ret = call i64 @llvm.riscv.sc.d(i64 %v, ptr %src, i32 3)
+ ret i64 %ret
+}
diff --git a/llvm/test/CodeGen/RISCV/zawrs.ll b/llvm/test/CodeGen/RISCV/zawrs.ll
new file mode 100644
index 0000000000000..fa45f049ea818
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zawrs.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zawrs -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+zawrs -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64
+
+define void @wrs_nto() {
+; RV32-LABEL: wrs_nto:
+; RV32: # %bb.0:
+; RV32-NEXT: wrs.nto
+; RV32-NEXT: ret
+;
+; RV64-LABEL: wrs_nto:
+; RV64: # %bb.0:
+; RV64-NEXT: wrs.nto
+; RV64-NEXT: ret
+ call void @llvm.riscv.wrs.nto()
+ ret void
+}
+
+define void @wrs_sto() {
+; RV32-LABEL: wrs_sto:
+; RV32: # %bb.0:
+; RV32-NEXT: wrs.nto
+; RV32-NEXT: ret
+;
+; RV64-LABEL: wrs_sto:
+; RV64: # %bb.0:
+; RV64-NEXT: wrs.nto
+; RV64-NEXT: ret
+ call void @llvm.riscv.wrs.sto()
+ ret void
+}
>From 22c9d507d256725d14499b4e3c380df71968b0ab Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Thu, 6 Jun 2024 14:39:02 +0800
Subject: [PATCH 2/4] Rename
Created using spr 1.3.6-beta.1
---
clang/lib/Headers/CMakeLists.txt | 2 +-
clang/lib/Headers/riscv_atomics.h | 36 -------------------
.../RISCV/atomics-intrinsics/zalrsc-error.c | 2 +-
.../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 34 +++++++++---------
.../CodeGen/RISCV/atomics-intrinsics/zawrs.c | 2 +-
5 files changed, 20 insertions(+), 56 deletions(-)
delete mode 100644 clang/lib/Headers/riscv_atomics.h
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index cf2fbf1893772..ee684c5225ed5 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,7 +118,7 @@ set(ppc_htm_files
)
set(riscv_files
- riscv_atomics.h
+ riscv_atomic.h
riscv_bitmanip.h
riscv_crypto.h
riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h
b/clang/lib/Headers/riscv_atomics.h
deleted file mode 100644
index 35db57fe36131..0000000000000
--- a/clang/lib/Headers/riscv_atomics.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*===---- riscv_atomics.h - RISC-V atomics intrinsics ----------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#ifndef __RISCV_ATOMICS_H
-#define __RISCV_ATOMICS_H
-
-#ifdef __riscv_zalrsc
-enum {
- __RISCV_ORDER_NONE = 0,
- __RISCV_ORDER_AQ = 1,
- __RISCV_ORDER_RL = 2,
- __RISCV_ORDER_AQ_RL = 3
-};
-
-#define __riscv_lr_w __builtin_riscv_lr_w
-#define __riscv_sc_w __builtin_riscv_sc_w
-
-#if __riscv_xlen == 64
-#define __riscv_lr_d __builtin_riscv_lr_d
-#define __riscv_sc_d __builtin_riscv_sc_d
-#endif
-
-#endif
-
-#ifdef __riscv_zawrs
-#define __riscv_wrs_nto __builtin_riscv_wrs_nto
-#define __riscv_wrs_sto __builtin_riscv_wrs_sto
-#endif
-
-#endif
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
b/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
index d274077c9acfd..0e7bf86f7f156 100644
--- a/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
@@ -2,7 +2,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +zalrsc -S -verify %s -o -
// RUN: %clang_cc1 -triple riscv64 -target-feature +zalrsc -S -verify %s -o -
-#include <riscv_atomics.h>
+#include <riscv_atomic.h>
int zalrsc_lr_w(int* ptr) {
return __riscv_lr_w(ptr, 4); // expected-error {{argument value 4 is outside
the valid range [0, 3]}}
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
b/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
index 662ac53ee1e57..e128484ae5a9e 100644
--- a/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
@@ -8,7 +8,7 @@
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <stdint.h>
-#include <riscv_atomics.h>
+#include <riscv_atomic.h>
// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_lr_w_none
// CHECK-RV32-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
@@ -23,7 +23,7 @@
// CHECK-RV64-NEXT: ret i32 [[TMP0]]
//
int zalrsc_lr_w_none(int* ptr) {
- return __riscv_lr_w(ptr, __RISCV_ORDER_NONE);
+ return __riscv_lr_w(ptr, __RISCV_ORDERING_NONE);
}
// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_lr_w_aq
@@ -39,7 +39,7 @@ int zalrsc_lr_w_none(int* ptr) {
// CHECK-RV64-NEXT: ret i32 [[TMP0]]
//
int zalrsc_lr_w_aq(int* ptr) {
- return __riscv_lr_w(ptr, __RISCV_ORDER_AQ);
+ return __riscv_lr_w(ptr, __RISCV_ORDERING_AQ);
}
// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_lr_w_rl
@@ -55,7 +55,7 @@ int zalrsc_lr_w_aq(int* ptr) {
// CHECK-RV64-NEXT: ret i32 [[TMP0]]
//
int zalrsc_lr_w_rl(int* ptr) {
- return __riscv_lr_w(ptr, __RISCV_ORDER_RL);
+ return __riscv_lr_w(ptr, __RISCV_ORDERING_RL);
}
// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_lr_w_aqrl
@@ -71,7 +71,7 @@ int zalrsc_lr_w_rl(int* ptr) {
// CHECK-RV64-NEXT: ret i32 [[TMP0]]
//
int zalrsc_lr_w_aqrl(int* ptr) {
- return __riscv_lr_w(ptr, __RISCV_ORDER_AQ_RL);
+ return __riscv_lr_w(ptr, __RISCV_ORDERING_AQ_RL);
}
// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_sc_w_none
@@ -87,7 +87,7 @@ int zalrsc_lr_w_aqrl(int* ptr) {
// CHECK-RV64-NEXT: ret i32 [[TMP0]]
//
int zalrsc_sc_w_none(int v, int* ptr) {
- return __riscv_sc_w(v, ptr, __RISCV_ORDER_NONE);
+ return __riscv_sc_w(v, ptr, __RISCV_ORDERING_NONE);
}
// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_sc_w_aq
@@ -103,7 +103,7 @@ int zalrsc_sc_w_none(int v, int* ptr) {
// CHECK-RV64-NEXT: ret i32 [[TMP0]]
//
int zalrsc_sc_w_aq(int v, int* ptr) {
- return __riscv_sc_w(v, ptr, __RISCV_ORDER_AQ);
+ return __riscv_sc_w(v, ptr, __RISCV_ORDERING_AQ);
}
// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_sc_w_rl
@@ -119,7 +119,7 @@ int zalrsc_sc_w_aq(int v, int* ptr) {
// CHECK-RV64-NEXT: ret i32 [[TMP0]]
//
int zalrsc_sc_w_rl(int v, int* ptr) {
- return __riscv_sc_w(v, ptr, __RISCV_ORDER_RL);
+ return __riscv_sc_w(v, ptr, __RISCV_ORDERING_RL);
}
// CHECK-RV32-LABEL: define dso_local i32 @zalrsc_sc_w_aqrl
@@ -135,7 +135,7 @@ int zalrsc_sc_w_rl(int v, int* ptr) {
// CHECK-RV64-NEXT: ret i32 [[TMP0]]
//
int zalrsc_sc_w_aqrl(int v, int* ptr) {
- return __riscv_sc_w(v, ptr, __RISCV_ORDER_AQ_RL);
+ return __riscv_sc_w(v, ptr, __RISCV_ORDERING_AQ_RL);
}
#if __riscv_xlen == 64
@@ -146,7 +146,7 @@ int zalrsc_sc_w_aqrl(int v, int* ptr) {
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
//
int64_t zalrsc_lr_d_none(int64_t* ptr) {
- return __riscv_lr_d(ptr, __RISCV_ORDER_NONE);
+ return __riscv_lr_d(ptr, __RISCV_ORDERING_NONE);
}
// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_lr_d_aq
@@ -156,7 +156,7 @@ int64_t zalrsc_lr_d_none(int64_t* ptr) {
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
//
int64_t zalrsc_lr_d_aq(int64_t* ptr) {
- return __riscv_lr_d(ptr, __RISCV_ORDER_AQ);
+ return __riscv_lr_d(ptr, __RISCV_ORDERING_AQ);
}
// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_lr_d_rl
@@ -166,7 +166,7 @@ int64_t zalrsc_lr_d_aq(int64_t* ptr) {
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
//
int64_t zalrsc_lr_d_rl(int64_t* ptr) {
- return __riscv_lr_d(ptr, __RISCV_ORDER_RL);
+ return __riscv_lr_d(ptr, __RISCV_ORDERING_RL);
}
// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_lr_d_aqrl
@@ -176,7 +176,7 @@ int64_t zalrsc_lr_d_rl(int64_t* ptr) {
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
//
int64_t zalrsc_lr_d_aqrl(int64_t* ptr) {
- return __riscv_lr_d(ptr, __RISCV_ORDER_AQ_RL);
+ return __riscv_lr_d(ptr, __RISCV_ORDERING_AQ_RL);
}
// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_sc_d_none
@@ -186,7 +186,7 @@ int64_t zalrsc_lr_d_aqrl(int64_t* ptr) {
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
//
int64_t zalrsc_sc_d_none(int64_t v, int64_t* ptr) {
- return __riscv_sc_d(v, ptr, __RISCV_ORDER_NONE);
+ return __riscv_sc_d(v, ptr, __RISCV_ORDERING_NONE);
}
// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_sc_d_aq
@@ -196,7 +196,7 @@ int64_t zalrsc_sc_d_none(int64_t v, int64_t* ptr) {
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
//
int64_t zalrsc_sc_d_aq(int64_t v, int64_t* ptr) {
- return __riscv_sc_d(v, ptr, __RISCV_ORDER_AQ);
+ return __riscv_sc_d(v, ptr, __RISCV_ORDERING_AQ);
}
// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_sc_d_rl
@@ -206,7 +206,7 @@ int64_t zalrsc_sc_d_aq(int64_t v, int64_t* ptr) {
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
//
int64_t zalrsc_sc_d_rl(int64_t v, int64_t* ptr) {
- return __riscv_sc_d(v, ptr, __RISCV_ORDER_RL);
+ return __riscv_sc_d(v, ptr, __RISCV_ORDERING_RL);
}
// CHECK-RV64-LABEL: define dso_local i64 @zalrsc_sc_d_aqrl
@@ -216,7 +216,7 @@ int64_t zalrsc_sc_d_rl(int64_t v, int64_t* ptr) {
// CHECK-RV64-NEXT: ret i64 [[TMP0]]
//
int64_t zalrsc_sc_d_aqrl(int64_t v, int64_t* ptr) {
- return __riscv_sc_d(v, ptr, __RISCV_ORDER_AQ_RL);
+ return __riscv_sc_d(v, ptr, __RISCV_ORDERING_AQ_RL);
}
#endif
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
index 998655e67a160..22996e57893c0 100644
--- a/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
@@ -7,7 +7,7 @@
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
-#include <riscv_atomics.h>
+#include <riscv_atomic.h>
// CHECK-RV32-LABEL: define dso_local void @zawrs_nto
// CHECK-RV32-SAME: () #[[ATTR0:[0-9]+]] {
>From ce5f6c01768feaa6eb6a2d6554e135e3449125d8 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Thu, 6 Jun 2024 15:01:10 +0800
Subject: [PATCH 3/4] Add missing change
Created using spr 1.3.6-beta.1
---
clang/lib/Headers/riscv_atomic.h | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 clang/lib/Headers/riscv_atomic.h
diff --git a/clang/lib/Headers/riscv_atomic.h b/clang/lib/Headers/riscv_atomic.h
new file mode 100644
index 0000000000000..517fe043b037c
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomic.h
@@ -0,0 +1,36 @@
+/*===---- riscv_atomic.h - RISC-V atomic intrinsics ------------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __RISCV_ATOMIC_H
+#define __RISCV_ATOMIC_H
+
+#ifdef __riscv_zalrsc
+enum {
+ __RISCV_ORDERING_NONE = 0,
+ __RISCV_ORDERING_AQ = 1,
+ __RISCV_ORDERING_RL = 2,
+ __RISCV_ORDERING_AQ_RL = 3
+};
+
+#define __riscv_lr_w __builtin_riscv_lr_w
+#define __riscv_sc_w __builtin_riscv_sc_w
+
+#if __riscv_xlen == 64
+#define __riscv_lr_d __builtin_riscv_lr_d
+#define __riscv_sc_d __builtin_riscv_sc_d
+#endif
+
+#endif
+
+#ifdef __riscv_zawrs
+#define __riscv_wrs_nto __builtin_riscv_wrs_nto
+#define __riscv_wrs_sto __builtin_riscv_wrs_sto
+#endif
+
+#endif
>From 7b008d4b7ba711d82ca7a3ee4f4e5121d3f1d8f7 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng...@bytedance.com>
Date: Fri, 7 Jun 2024 12:05:44 +0800
Subject: [PATCH 4/4] Remove test files and add rv64 test for lr/sc w
Created using spr 1.3.6-beta.1
---
.../test/CodeGen/RISCV/{zalrsc-rv64.ll => zalrsc-d-intrinsic.ll} | 0
.../test/CodeGen/RISCV/{zalrsc-rv32.ll => zalrsc-w-intrinsic.ll} | 1 +
llvm/test/CodeGen/RISCV/{zawrs.ll => zawrs-intrinsic.ll} | 0
3 files changed, 1 insertion(+)
rename llvm/test/CodeGen/RISCV/{zalrsc-rv64.ll => zalrsc-d-intrinsic.ll} (100%)
rename llvm/test/CodeGen/RISCV/{zalrsc-rv32.ll => zalrsc-w-intrinsic.ll} (95%)
rename llvm/test/CodeGen/RISCV/{zawrs.ll => zawrs-intrinsic.ll} (100%)
diff --git a/llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
b/llvm/test/CodeGen/RISCV/zalrsc-d-intrinsic.ll
similarity index 100%
rename from llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
rename to llvm/test/CodeGen/RISCV/zalrsc-d-intrinsic.ll
diff --git a/llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
b/llvm/test/CodeGen/RISCV/zalrsc-w-intrinsic.ll
similarity index 95%
rename from llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
rename to llvm/test/CodeGen/RISCV/zalrsc-w-intrinsic.ll
index f71836fb553aa..53f1106844dd0 100644
--- a/llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/zalrsc-w-intrinsic.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s |
FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s |
FileCheck %s
define i32 @lr_w_none(ptr %src) {
; CHECK-LABEL: lr_w_none:
diff --git a/llvm/test/CodeGen/RISCV/zawrs.ll
b/llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll
similarity index 100%
rename from llvm/test/CodeGen/RISCV/zawrs.ll
rename to llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
