https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/19] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -1949,24 +1949,36 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
+const SPIRVType *ResType,
+
@@ -1949,24 +1949,36 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
+const SPIRVType *ResType,
+
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/18] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
@@ -1949,24 +1949,36 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
+const SPIRVType *ResType,
+
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/115902
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@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
https://github.com/farzonl approved this pull request.
lgtm
https://github.com/llvm/llvm-project/pull/115902
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@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/18] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/115902
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@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
@@ -2826,6 +2843,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
+ case Intrin
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/16] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/15] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -2826,6 +2843,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
+ case Intrin
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -2826,6 +2843,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
+ case Intrin
@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/115902
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https://github.com/Keenuts commented:
Thanks for this addition! Sorry late review,missed that
https://github.com/llvm/llvm-project/pull/115902
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@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -2206,6 +2206,15 @@ float4 trunc(float4);
// Wave* builtins
//===--===//
+/// \brief Returns true if the expression is true in any active lane in the
+/// current wave.
+///
+/// \param Val The boolean exp
@@ -4744,6 +4744,12 @@ def HLSLAny : LangBuiltin<"HLSL_LANG"> {
let Prototype = "bool(...)";
}
+def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> {
+ let Spellings = ["__builtin_hlsl_wave_active_any_true"];
+ let Attributes = [NoThrow, Const];
+ let Prototype = "bool(b
@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -2206,6 +2206,15 @@ float4 trunc(float4);
// Wave* builtins
//===--===//
+/// \brief Returns true if the expression is true in any active lane in the
+/// current wave.
+///
+/// \param Val The boolean exp
@@ -630,6 +630,15 @@ void RequirementHandler::initAvailableCapabilities(const
SPIRVSubtarget &ST) {
addAvailableCaps({Capability::Shader, Capability::Linkage, Capability::Int8,
Capability::Int16});
+ if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3)))
---
@@ -94,6 +94,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
@@ -630,6 +630,15 @@ void RequirementHandler::initAvailableCapabilities(const
SPIRVSubtarget &ST) {
addAvailableCaps({Capability::Shader, Capability::Linkage, Capability::Int8,
Capability::Int16});
+ if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3)))
---
@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -94,6 +94,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
@@ -2206,6 +2206,15 @@ float4 trunc(float4);
// Wave* builtins
//===--===//
+/// \brief Returns true if the expression is true in any active lane in the
+/// current wave.
+///
+/// \param Val The boolean exp
https://github.com/pow2clk approved this pull request.
Thanks for the fixups!
https://github.com/llvm/llvm-project/pull/115902
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https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/13] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/12] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -finclude-default-header
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK: %[[#bool:]] = OpTypeBool
+; CHECK: %[[#uint:]] = OpType
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK: %[[#bool:]] = OpTypeBool
+; CHECK: %[[#uint:]] = OpType
@@ -1995,7 +2014,7 @@ bool
SPIRVInstructionSelector::selectWaveReadLaneAt(Register ResVReg,
TII.get(SPIRV::OpGroupNonUniformShuffle))
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType))
- .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII))
+
@@ -1949,6 +1952,22 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -finclude-default-header
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/11] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/11] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/9] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/115902
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@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
@@ -94,6 +94,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
@@ -853,6 +853,15 @@ def CreateHandleFromBinding : DXILOp<217,
createHandleFromBinding> {
let stages = [Stages];
}
+def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
+ let Doc = "returns true if the expression is true in any of the active lanes
in the current wave";
+ l
@@ -19120,6 +19120,15 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
ArrayRef{Op0, Op1}, nullptr, "hlsl.step");
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+Val
https://github.com/inbelic approved this pull request.
LGTM., just some minor fix-ups
https://github.com/llvm/llvm-project/pull/115902
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@@ -676,7 +679,6 @@ void RequirementHandler::initAvailableCapabilitiesForOpenCL(
addAvailableCaps({Capability::SubgroupDispatch, Capability::PipeStorage});
if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3)))
addAvailableCaps({Capability::GroupNonUniform,
in
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/8] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/8] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
@@ -93,6 +93,7 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32
@@ -93,6 +93,7 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/6] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/5] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
@@ -93,6 +93,7 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify
+
+bool test_too_few_arg() {
+ return __builtin_hlsl_wave_active_any_true();
+ // expected-error@-1 {{too few arguments to functi
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/4] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
V-FEXrt wrote:
do you mean `-mtriple=spirv32v1.5-unknown-unknown`? I couldn't get any other
variant of the `spirv` part to work
https://github.com
@@ -19108,6 +19108,21 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
ArrayRef{Op0, Op1}, nullptr, "hlsl.step");
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+Int
https://github.com/V-FEXrt edited
https://github.com/llvm/llvm-project/pull/115902
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@@ -19108,6 +19108,21 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
ArrayRef{Op0, Op1}, nullptr, "hlsl.step");
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+Int
@@ -1920,6 +1923,24 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/115902
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https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/115902
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@@ -2091,6 +2091,12 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned
BuiltinID, CallExpr *TheCall) {
return true;
break;
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+if (SemaRef.checkArgCount(TheCall, 1))
+ return true;
+
+break;
+
https://github.com/inbelic commented:
Nice work. Mostly just some nits and cleanups :)
https://github.com/llvm/llvm-project/pull/115902
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@@ -202,6 +202,7 @@ defset list OpClasses = {
def unpack4x8 : DXILOpClass;
def viewID : DXILOpClass;
def waveActiveAllEqual : DXILOpClass;
+ def waveActiveAnyTrue : DXILOpClass;
inbelic wrote:
You shouldn't define and use this, instead use `waveAnyTrue`
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -fnative-half-type
-triple \
inbelic wrote:
I think we can remove the `-std=hlsl2021` flags.
https://github.com/llvm/llvm-project/pull/115902
___
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
inbelic wrote:
I think we prefer `-mtriple=spirv-unknown-unknown`. You might need to use
`spirv1.[5|6]` if you are using an new included spirv op.
@@ -19108,6 +19108,21 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
ArrayRef{Op0, Op1}, nullptr, "hlsl.step");
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+Int
@@ -93,6 +93,7 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/3] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Ashley Coleman (V-FEXrt)
Changes
Resolves https://github.com/llvm/llvm-project/issues/99160
- [x] Implement `WaveActiveAnyTrue` clang builtin,
- [x] Link `WaveActiveAnyTrue` clang builtin with `hlsl_intrinsics.h`
- [x] Add sem
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https://github.com/V-FEXrt created
https://github.com/llvm/llvm-project/pull/115902
Resolves https://github.com/llvm/llvm-project/issues/99160
- [x] Implement `WaveActiveAnyTrue` clang builtin,
- [x] Link `WaveActiveAnyTrue` clang builtin with `hlsl_intrinsics.h`
- [x] Add sema checks for `W
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