[PATCH] D89301: [X86] Add user-level interrupt instructions

2020-10-20 Thread Wang Tianqing via Phabricator via cfe-commits
tianqing updated this revision to Diff 299317. tianqing added a comment. Herald added a subscriber: dexonsmith. Address review comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89301/new/ https://reviews.llvm.org/D89301 Files: clang/docs/C

[PATCH] D89301: [X86] Add user-level interrupt instructions

2020-10-18 Thread Pengfei Wang via Phabricator via cfe-commits
pengfei added a comment. You need to add test for macro UINTR in clang/test/Preprocessor/predefined-arch-macros.c for SapphireRapids. Comment at: llvm/docs/ReleaseNotes.rst:117 the target CPU. -* Support for ISA HRESET has been added. +* Support for HRESET and UINTR instru

[PATCH] D89301: [X86] Add user-level interrupt instructions

2020-10-18 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86InstrInfo.td:320 +def X86testui : SDNode<"X86ISD::TESTUI", + SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, [SDNPHasChain]>; I think this should have SDNPSideEffect to match

[PATCH] D89301: [X86] Add user-level interrupt instructions

2020-10-13 Thread Wang Tianqing via Phabricator via cfe-commits
tianqing created this revision. Herald added subscribers: llvm-commits, cfe-commits, dang, hiraditya, mgorny. Herald added projects: clang, LLVM. tianqing requested review of this revision. For more details about these instructions, please refer to the latest ISE document: https://software.intel.c