[PATCH] D63417: [RISCV] Specify registers used for exception handling

2019-07-08 Thread Alex Bradbury via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL365305: [RISCV] Specify registers used for exception handling (authored by asb, committed by ). Herald added subscribers: llvm-commits, lenary, MaskRay. Herald added a project: LLVM. Changed prior to comm

[PATCH] D63417: [RISCV] Specify registers used for exception handling

2019-07-03 Thread Alex Bradbury via Phabricator via cfe-commits
asb added a comment. Ed, if you haven't already could you request commit access so you can commit these approved patches yourself? See https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access for details. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://revie

[PATCH] D63417: [RISCV] Specify registers used for exception handling

2019-07-03 Thread Edward Jones via Phabricator via cfe-commits
edward-jones updated this revision to Diff 207769. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://reviews.llvm.org/D63417 Files: lib/Basic/Targets/RISCV.h test/CodeGen/builtins-riscv.c Index: test/CodeGen/builtins-riscv.c ==

[PATCH] D63417: [RISCV] Specify registers used for exception handling

2019-07-03 Thread Alex Bradbury via Phabricator via cfe-commits
asb added inline comments. Comment at: test/CodeGen/builtins-riscv.c:4 + +void test_eh_return_data_regno() +{ Nit: having `{` on this line would be more consistent with usual LLVM style CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://r

[PATCH] D63417: [RISCV] Specify registers used for exception handling

2019-07-03 Thread Alex Bradbury via Phabricator via cfe-commits
asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks, looks good to me! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://reviews.llvm.org/D63417 ___ cfe-commits mailing lis

[PATCH] D63417: [RISCV] Specify registers used for exception handling

2019-07-03 Thread Edward Jones via Phabricator via cfe-commits
edward-jones updated this revision to Diff 207736. edward-jones added a comment. Add riscv64 target run line, renamed test file to builtins-riscv.c, and rebased. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://reviews.llvm.org/D63417 Files: lib/Basic/Targets/RISCV.h

[PATCH] D63417: [RISCV] Specify registers used for exception handling

2019-07-02 Thread Alex Bradbury via Phabricator via cfe-commits
asb requested changes to this revision. asb added a comment. This revision now requires changes to proceed. Could you please add a riscv64 RUN line too, for completeness? Other archs seem to call the equivalent test file `builtins-archname.c` rather than `builtin-archname.c`, so I'd adjust the n

[PATCH] D63417: [RISCV] Specify registers used for exception handling

2019-06-19 Thread Edward Jones via Phabricator via cfe-commits
edward-jones updated this revision to Diff 205542. edward-jones retitled this revision from "[WIP][RISCV] Specify registers used for exception handling" to "[RISCV] Specify registers used for exception handling". edward-jones edited the summary of this revision. edward-jones added a comment. Add