[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 488924. 4vtomat added a comment. NFC, refactoring the code. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-target-features.c

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 488918. 4vtomat added a comment. NFC Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.r

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 488916. 4vtomat marked 8 inline comments as done. 4vtomat added a comment. [NFC] Refactor the code. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/tes

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 486169. 4vtomat added a comment. Address Eric's comments! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-target-features.c l

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

ego added a comment. FYI, more issues with v0 not being accepted as an operand with unmasked instructions. Comment at: llvm/test/MC/RISCV/rvv/rv64zvkns.s:59 + +vaeskf1.vi v10, v9, 1 +# CHECK-INST: vaeskf1.vi v10, v9, 1 ego wrote: > craig.topper wrote: > > ego

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

ego added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:135 + defm VANDN_V : VALU_IV_V_X_I<"vandn", 0b01>; + def VBREV8_V : VALUVs2<0b010010, 0b01000, OPIVV, "vbrev8.v">; + defm VCLMUL_V : VALU_IV_V_X_VCLMUL<"vclmul", 0b001100>; T

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Comment at: llvm/test/MC/RISCV/rvv/rv64zvkns.s:59 + +vaeskf1.vi v10, v9, 1 +# CHECK-INST: vaeskf1.vi v10, v9, 1 ego wrote: > If I replaces "v10" with "v0", the test fails with an assertion failure. My > own patch uses a slight

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:97 bool HasRV32 = false; + bool HasStdExtZvkb = false; + bool HasStdExtZvkg = false; This needs to be rebased, it's all autogenerated by tablegen now. Repository: rG L

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

ego added a comment. See my comment below where I can trigger an MC-layer assertion when using "vaeskf1 v0, ...". Comment at: llvm/test/MC/RISCV/rvv/rv64zvkns.s:1-9 +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s \ +# RUN:

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 484226. 4vtomat added a comment. Correct OPERAND_LAST_RISCV_IMM in OperandType Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

kito-cheng added a comment. Ken has updated spec to clarify requirements of those vector crypto extensions: https://github.com/riscv/riscv-crypto/commit/40695306f628e6dc764d1d0f35392eac792d2c3b These Vector Crypto Extensions can be built on any RISC-V base. However, XLEN=32 implementations

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 484224. 4vtomat added a comment. Address Eop's comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-target-features.c llv

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 484217. 4vtomat added a comment. Update to final draft 20221208 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-target-features

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

eopXD added inline comments. Comment at: llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s:1 +# RUN: not llvm-mc -triple=riscv64 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \ +# RUN:| FileCheck %s --check-prefix=CHECK-ERROR I see simila

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

eopXD added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:772 + + if ((Exts.count("zvkb") || Exts.count("zvknhb")) && !Exts.count("zve64x")) +return createStringError( With this check, the check for these extensions on top are redundant. =

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 484154. 4vtomat marked 22 inline comments as done. 4vtomat added a comment. Replace llvm/test/MC/RISCV/rvv/rv64zvknhb.s and llvm/test/MC/RISCV/rvv/rv64zvknhb.s with a single llvm/test/MC/RISCV/rvv/rv64zvknh.s Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 483884. 4vtomat added a comment. Address most of Eric's comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-target-featur

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

ego added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:827 +{{"zvkg"}, {ImpliedExtsZve32x}}, +{{"zvknha"}, {ImpliedExtsZve32x}}, +{{"zvknhb"}, {ImpliedExtsZve64x}}, ego wrote: > How does this work? This doesn't seem to be enough, > "

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

ego added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:827 +{{"zvkb"}, {ImpliedExtsZve64x}}, +{{"zvkg"}, {ImpliedExtsZve32x}}, +{{"zvknha"}, {ImpliedExtsZve32x}}, craig.topper wrote: > ego wrote: > > What is the reasoning between 32

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

asb added a comment. I just wanted to document the discussion we had in the RISC-V sync call yesterday. There were no objections to treating the vector crypto work like any other experimental extension, per our current policy (I think the main reason people might object is if substantial churn

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 481540. 4vtomat added a comment. Address Eric Gouriou's comments, thanks for reviewing. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocess

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:827 +{{"zvkb"}, {ImpliedExtsZve64x}}, +{{"zvkg"}, {ImpliedExtsZve32x}}, +{{"zvknha"}, {ImpliedExtsZve32x}}, ego wrote: > What is the reasoning between 32 vs 64 for those

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

ego added a comment. I have been working on a patch set to support Zvk. It will take me a few more days to prepare my patches to post them publicly. Your patches are in a very good shape and a lot of files end up looking pretty similar. I have a few comments, most minor. This is my first review

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 480320. 4vtomat added a comment. Resolved Craig's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocessor/riscv-target-features.c l

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat added a comment. In D138807#3972441 , @craig.topper wrote: > In D138807#3962417 , @craig.topper > wrote: > >> Anything that uses OP-P needs to have a DecoderNamespace assigned and >> RISCVDisassembler::

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added a comment. In D138807#3962417 , @craig.topper wrote: > Anything that uses OP-P needs to have a DecoderNamespace assigned and > RISCVDisassembler::getInstruction will need to lookup that table when V/Zve > is enabled. Otherwise we wil

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added a comment. Anything that uses OP-P needs to have a DecoderNamespace assigned and RISCVDisassembler::getInstruction will need to lookup that table when V/Zve is enabled. Otherwise we will have a conflict if the P extension is ever commited to LLVM. Comment

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

4vtomat updated this revision to Diff 479142. 4vtomat added a comment. Fixed the comment from Craig Topper and Philip Reames Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 Files: clang/test/Preprocesso

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

reames added a comment. Some very high level comments for the moment. Until the spec is frozen, these need to be moved into the experimental namespace. You should also add a mention of them under the experimental list in docs/RISCVUsage. A link to the current spec version - along with an exac

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:827 {{"zvfh"}, {ImpliedExtsZvfh}}, +{{"zvkb"}, {ImpliedExtsV}}, +{{"zvkg"}, {ImpliedExtsV}}, Does Crypto really require V or could it work with Zve? Repository: rG

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added a comment. Can you link to a specification? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138807/new/ https://reviews.llvm.org/D138807 ___ cfe-commits mailing list cfe-commits@lists.ll

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

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