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zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso,
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD,
MaskRay.
Herald added projects: clang, LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D138807
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rvv/rv64zvkb.s
llvm/test/MC/RISCV/rvv/rv64zvkg.s
llvm/test/MC/RISCV/rvv/rv64zvknf.s
llvm/test/MC/RISCV/rvv/rv64zvknha.s
llvm/test/MC/RISCV/rvv/rv64zvknhb.s
llvm/test/MC/RISCV/rvv/rv64zvkns.s
llvm/test/MC/RISCV/rvv/rv64zvksed.s
llvm/test/MC/RISCV/rvv/rv64zvksh.s
Index: llvm/test/MC/RISCV/rvv/rv64zvksh.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvksh %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvksh %s \
+# RUN: | llvm-objdump -d --mattr=+zvksh - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvksh %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x57,0xb5,0x93,0xd6]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 57 b5 93 d6 <unknown>
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 57 35 94 da <unknown>
Index: llvm/test/MC/RISCV/rvv/rv64zvksed.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvksed %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvksed %s \
+# RUN: | llvm-objdump -d --mattr=+zvksed - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvksed %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x57,0xb5,0x93,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 57 b5 93 ea <unknown>
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x57,0x35,0x90,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 57 35 90 ee <unknown>
Index: llvm/test/MC/RISCV/rvv/rv64zvkns.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns.s
@@ -0,0 +1,87 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvkns %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvkns %s \
+# RUN: | llvm-objdump -d --mattr=+zvkns - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvkns %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vaesdf.vv v10, v9
+# CHECK-INST: vaesdf.vv v10, v9
+# CHECK-ENCODING: [0x57,0x05,0x90,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 05 90 ee <unknown>
+
+vaesdf.vs v10, v9
+# CHECK-INST: vaesdf.vs v10, v9
+# CHECK-ENCODING: [0x57,0x65,0x90,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 65 90 66 <unknown>
+
+vaesef.vv v10, v9
+# CHECK-INST: vaesef.vv v10, v9
+# CHECK-ENCODING: [0x57,0x05,0x90,0xf6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 05 90 f6 <unknown>
+
+vaesef.vs v10, v9
+# CHECK-INST: vaesef.vs v10, v9
+# CHECK-ENCODING: [0x57,0x65,0x90,0x76]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 65 90 76 <unknown>
+
+vaesdm.vv v10, v9
+# CHECK-INST: vaesdm.vv v10, v9
+# CHECK-ENCODING: [0x57,0x45,0x90,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 45 90 ee <unknown>
+
+vaesdm.vs v10, v9
+# CHECK-INST: vaesdm.vs v10, v9
+# CHECK-ENCODING: [0x57,0x65,0x90,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 65 90 6a <unknown>
+
+vaesem.vv v10, v9
+# CHECK-INST: vaesem.vv v10, v9
+# CHECK-ENCODING: [0x57,0x45,0x90,0xf6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 45 90 f6 <unknown>
+
+vaesem.vs v10, v9
+# CHECK-INST: vaesem.vs v10, v9
+# CHECK-ENCODING: [0x57,0x65,0x90,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 65 90 7a <unknown>
+
+vaeskf1.vi v10, v9, 0, v0.t
+# CHECK-INST: vaeskf1.vi v10, v9, 0, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x90,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 05 90 f8 <unknown>
+
+vaeskf2.vi v10, v9, 0, v0.t
+# CHECK-INST: vaeskf2.vi v10, v9, 0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x90,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 45 90 f8 <unknown>
+
+vaeskr1.vi v10, v9, 0, v0.t
+# CHECK-INST: vaeskr1.vi v10, v9, 0, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x90,0xfc]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 05 90 fc <unknown>
+
+vaeskr2.vi v10, v9, 0
+# CHECK-INST: vaeskr2.vi v10, v9, 0
+# CHECK-ENCODING: [0x57,0x45,0x90,0xfe]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 45 90 fe <unknown>
+
+vaesz.vs v10, v9
+# CHECK-INST: vaesz.vs v10, v9
+# CHECK-ENCODING: [0x57,0x65,0x90,0x7e]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 65 90 7e <unknown>
Index: llvm/test/MC/RISCV/rvv/rv64zvknhb.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvknhb.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvknhb %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvknhb %s \
+# RUN: | llvm-objdump -d --mattr=+zvknhb - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvknhb %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsha2ms.vv v10, v9, v8
+# CHECK-INST: vsha2ms.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xf6]
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
+# CHECK-UNKNOWN: 57 35 94 f6 <unknown>
+
+vsha2ch.vv v10, v9, v8
+# CHECK-INST: vsha2ch.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
+# CHECK-UNKNOWN: 57 35 94 fa <unknown>
+
+vsha2cl.vv v10, v9, v8
+# CHECK-INST: vsha2cl.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
+# CHECK-UNKNOWN: 57 35 94 f2 <unknown>
Index: llvm/test/MC/RISCV/rvv/rv64zvknha.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvknha.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvknha %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvknha %s \
+# RUN: | llvm-objdump -d --mattr=+zvknha - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvknha %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsha2ms.vv v10, v9, v8
+# CHECK-INST: vsha2ms.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xf6]
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
+# CHECK-UNKNOWN: 57 35 94 f6 <unknown>
+
+vsha2ch.vv v10, v9, v8
+# CHECK-INST: vsha2ch.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
+# CHECK-UNKNOWN: 57 35 94 fa <unknown>
+
+vsha2cl.vv v10, v9, v8
+# CHECK-INST: vsha2cl.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)) 'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))
+# CHECK-UNKNOWN: 57 35 94 f2 <unknown>
Index: llvm/test/MC/RISCV/rvv/rv64zvknf.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvknf.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvknf %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvknf %s \
+# RUN: | llvm-objdump -d --mattr=+zvknf - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvknf %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vaese128.vv v10, v9, v8
+# CHECK-INST: vaese128.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x05,0x94,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 05 94 f2 <unknown>
+
+vaese128.vs v10, v9, v8
+# CHECK-INST: vaese128.vs v10, v9, v8
+# CHECK-ENCODING: [0x57,0x65,0x94,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 65 94 6e <unknown>
+
+vaesd128.vv v10, v9, v8
+# CHECK-INST: vaesd128.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x05,0x94,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 05 94 ea <unknown>
+
+vaesd128.vs v10, v9, v8
+# CHECK-INST: vaesd128.vs v10, v9, v8
+# CHECK-ENCODING: [0x57,0x65,0x94,0x5e]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 65 94 5e <unknown>
+
+vaese256.vv v10, v9, v8
+# CHECK-INST: vaese256.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x45,0x94,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 45 94 f2 <unknown>
+
+vaese256.vs v10, v9, v8
+# CHECK-INST: vaese256.vs v10, v9, v8
+# CHECK-ENCODING: [0x57,0x65,0x94,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 65 94 72 <unknown>
+
+vaesd256.vv v10, v9, v8
+# CHECK-INST: vaesd256.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x45,0x94,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 45 94 ea <unknown>
+
+vaesd256.vs v10, v9, v8
+# CHECK-INST: vaesd256.vs v10, v9, v8
+# CHECK-ENCODING: [0x57,0x65,0x94,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 65 94 62 <unknown>
+
+vaes128k10.v v10, v9
+# CHECK-INST: vaes128k10.v v10, v9
+# CHECK-ENCODING: [0x57,0x05,0x90,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 05 90 e6 <unknown>
+
+vaes256k13.vv v10, v9, v8
+# CHECK-INST: vaes256k13.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x45,0x94,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 45 94 e6 <unknown>
+
+vaes256k14.vv v10, v9, v8
+# CHECK-INST: vaes256k14.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvknf'
+# CHECK-UNKNOWN: 57 35 94 e6 <unknown>
Index: llvm/test/MC/RISCV/rvv/rv64zvkg.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkg.s
@@ -0,0 +1,15 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvkg %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvkg %s \
+# RUN: | llvm-objdump -d --mattr=+zvkg - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvkg %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vghmac.vv v10, v9, v8
+# CHECK-INST: vghmac.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x05,0x94,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvkg'
+# CHECK-UNKNOWN: 57 05 94 d2 <unknown>
Index: llvm/test/MC/RISCV/rvv/rv64zvkb.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkb.s
@@ -0,0 +1,99 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvkb %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvkb %s \
+# RUN: | llvm-objdump -d --mattr=+zvkb - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvkb %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vandn.vv v10, v9, v8, v0.t
+# CHECK-INST: vandn.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 05 94 cc <unknown>
+
+vandn.vx v10, v9, a0, v0.t
+# CHECK-INST: vandn.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 95 cc <unknown>
+
+vandn.vi v10, v9, 7, v0.t
+# CHECK-INST: vandn.vi v10, v9, 7, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x93,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 b5 93 cc <unknown>
+
+vbrev8.v v10, v9, v0.t
+# CHECK-INST: vbrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x35,0x90,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 35 90 d0 <unknown>
+
+vclmul.vv v10, v9, v8
+# CHECK-INST: vclmul.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x05,0x94,0xd6]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 05 94 d6 <unknown>
+
+vclmul.vx v10, v9, a0
+# CHECK-INST: vclmul.vx v10, v9, a0
+# CHECK-ENCODING: [0x57,0x45,0x95,0xd6]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 95 d6 <unknown>
+
+vclmulh.vv v10, v9, v8
+# CHECK-INST: vclmulh.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x05,0x94,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 05 94 da <unknown>
+
+vclmulh.vx v10, v9, a0
+# CHECK-INST: vclmulh.vx v10, v9, a0
+# CHECK-ENCODING: [0x57,0x45,0x95,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 95 da <unknown>
+
+vrev8.v v10, v9, v0.t
+# CHECK-INST: vrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x90,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 90 d0 <unknown>
+
+vrol.vv v10, v9, v8, v0.t
+# CHECK-INST: vrol.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0xdc]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 05 94 dc <unknown>
+
+vrol.vx v10, v9, a0, v0.t
+# CHECK-INST: vrol.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0xdc]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 95 dc <unknown>
+
+vrol.vi v10, v9, 7, v0.t
+# CHECK-INST: vrol.vi v10, v9, 7, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x93,0xdc]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 b5 93 dc <unknown>
+
+vror.vv v10, v9, v8, v0.t
+# CHECK-INST: vror.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 05 94 e0 <unknown>
+
+vror.vx v10, v9, a0, v0.t
+# CHECK-INST: vror.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 45 95 e0 <unknown>
+
+vror.vi v10, v9, 7, v0.t
+# CHECK-INST: vror.vi v10, v9, 7, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x93,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvkb'
+# CHECK-UNKNOWN: 57 b5 93 e0 <unknown>
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -107,6 +107,30 @@
.attribute arch, "rv32izbc1p0"
# CHECK: attribute 5, "rv32i2p0_zbc1p0"
+.attribute arch, "rv32izvkns"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkns0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32izvknha"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknha0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32izvknhb"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknhb0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32izvknf"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknf0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32izvkb"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32izvkg"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkg0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32izvksed"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvksed0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32izvksh"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvksh0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+
.attribute arch, "rv32izbs1p0"
# CHECK: attribute 5, "rv32i2p0_zbs1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -40,6 +40,14 @@
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zvkns %s -o - | FileCheck --check-prefix=RV32ZVKNS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zvknf %s -o - | FileCheck --check-prefix=RV32ZVKNF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -82,6 +90,14 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zvkns %s -o - | FileCheck --check-prefix=RV64ZVKNS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zvknf %s -o - | FileCheck --check-prefix=RV64ZVKNF %s
+; RUN: llc -mtriple=riscv64 -mattr=+zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@@ -122,6 +138,14 @@
; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
+; RV32ZVKNS: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkns0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNHA: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknha0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNHB: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknha0p1_zvknhb0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNF: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknf0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKB: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKG: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkg0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvksed0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSH: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvksh0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -165,6 +189,14 @@
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
+; RV64ZVKNS: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkns0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNHA: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknha0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNHB: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknha0p1_zvknhb0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNF: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvknf0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKB: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKG: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkg0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKSED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvksed0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKSH: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvksh0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -94,6 +94,14 @@
bool HasStdExtZtso = false;
bool HasVendorXVentanaCondOps = false;
bool HasRV32 = false;
+ bool HasStdExtZvkns = false;
+ bool HasStdExtZvknha = false;
+ bool HasStdExtZvknhb = false;
+ bool HasStdExtZvknf = false;
+ bool HasStdExtZvkb = false;
+ bool HasStdExtZvkg = false;
+ bool HasStdExtZvksed = false;
+ bool HasStdExtZvksh = false;
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
@@ -188,6 +196,14 @@
bool hasStdExtZksed() const { return HasStdExtZksed; }
bool hasStdExtZksh() const { return HasStdExtZksh; }
bool hasStdExtZkr() const { return HasStdExtZkr; }
+ bool hasStdExtZvkns() const { return HasStdExtZvkns; }
+ bool hasStdExtZvknha() const { return HasStdExtZvknha; }
+ bool hasStdExtZvknhb() const { return HasStdExtZvknhb; }
+ bool hasStdExtZvknf() const { return HasStdExtZvknf; }
+ bool hasStdExtZvkb() const { return HasStdExtZvkb; }
+ bool hasStdExtZvkg() const { return HasStdExtZvkg; }
+ bool hasStdExtZvksed() const { return HasStdExtZvksed; }
+ bool hasStdExtZvksh() const { return HasStdExtZvksh; }
bool hasStdExtZicbom() const { return HasStdExtZicbom; }
bool hasStdExtZicboz() const { return HasStdExtZicboz; }
bool hasStdExtZicbop() const { return HasStdExtZicbop; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -0,0 +1,117 @@
+//===-- RISCVInstrInfoZvk.td - RISC-V 'Zvk' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+// This file describes the RISC-V instructions from the standard 'Zvk',
+// Vector Cryptography Instructions extension, version 0.1.
+///
+//===----------------------------------------------------------------------===//
+
+def rnum_0_7 : Operand<XLenVT>, ImmLeaf<XLenVT,
+ [{return (0 <= Imm && Imm <= 7);}]> {
+ let ParserMatchClass = UImmAsmOperand<5>;
+ let DecoderMethod = "decodeUImmOperand<5>";
+ let OperandType = "OPERAND_RVKRNUM";
+ let OperandNamespace = "RISCVOp";
+}
+
+def rnum_1_10 : Operand<XLenVT>, ImmLeaf<XLenVT,
+ [{return (1 <= Imm && Imm <= 10);}]> {
+ let ParserMatchClass = UImmAsmOperand<5>;
+ let DecoderMethod = "decodeUImmOperand<5>";
+ let OperandType = "OPERAND_RVKRNUM";
+ let OperandNamespace = "RISCVOp";
+}
+
+def rnum_1_14 : Operand<XLenVT>, ImmLeaf<XLenVT,
+ [{return (1 <= Imm && Imm <= 14);}]> {
+ let ParserMatchClass = UImmAsmOperand<5>;
+ let DecoderMethod = "decodeUImmOperand<5>";
+ let OperandType = "OPERAND_RVKRNUM";
+ let OperandNamespace = "RISCVOp";
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+class VALUVI_CUSTOM1<bits<6> funct6, string opcodestr, Operand optype>
+ : RVInstIVI<funct6, (outs VR:$vd),
+ (ins VR:$vs2, optype:$imm, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $imm$vm"> {
+ let Inst{14-12} = 0b000;
+}
+
+class VALUVI_CUSTOM2<bits<6> funct6, string opcodestr, Operand optype>
+ : RVInstIVI<funct6, (outs VR:$vd),
+ (ins VR:$vs2, optype:$imm, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $imm$vm"> {
+ let Inst{14-12} = 0b100;
+}
+
+class VALUVINoVm_CUSTOM1<bits<6> funct6, string opcodestr, Operand optype>
+ : VALUVINoVm<funct6, opcodestr, optype> {
+ let Inst{14-12} = 0b100;
+}
+}
+
+let Predicates = [HasStdExtZvknf] in {
+ def VAES128K10_V : VALUVs2NoVm<0b111001, 0b00000, RISCVVFormat<0b000>, "vaes128k10.v">;
+ def VAES256K13_VV : VALUVVNoVm<0b111001, RISCVVFormat<0b100>, "vaes256k13.vv">;
+ def VAES256K14_VV : VALUVVNoVm<0b111001, RISCVVFormat<0b011>, "vaes256k14.vv">;
+ def VAESD128_VV : VALUVVNoVm<0b111010, RISCVVFormat<0b000>, "vaesd128.vv">;
+ def VAESD128_VS : VALUVVNoVm<0b010111, RISCVVFormat<0b110>, "vaesd128.vs">;
+ def VAESD256_VV : VALUVVNoVm<0b111010, RISCVVFormat<0b100>, "vaesd256.vv">;
+ def VAESD256_VS : VALUVVNoVm<0b011000, RISCVVFormat<0b110>, "vaesd256.vs">;
+ def VAESE128_VV : VALUVVNoVm<0b111100, RISCVVFormat<0b000>, "vaese128.vv">;
+ def VAESE128_VS : VALUVVNoVm<0b011011, RISCVVFormat<0b110>, "vaese128.vs">;
+ def VAESE256_VV : VALUVVNoVm<0b111100, RISCVVFormat<0b100>, "vaese256.vv">;
+ def VAESE256_VS : VALUVVNoVm<0b011100, RISCVVFormat<0b110>, "vaese256.vs">;
+} // Predicates = [HasStdExtZvknf]
+
+let Predicates = [HasStdExtZvkns] in {
+ def VAESDF_VV : VALUVs2NoVm<0b111011, 0b00000, RISCVVFormat<0b000>, "vaesdf.vv">;
+ def VAESDF_VS : VALUVs2NoVm<0b011001, 0b00000, RISCVVFormat<0b110>, "vaesdf.vs">;
+ def VAESEF_VV : VALUVs2NoVm<0b111101, 0b00000, RISCVVFormat<0b000>, "vaesef.vv">;
+ def VAESEF_VS : VALUVs2NoVm<0b011101, 0b00000, RISCVVFormat<0b110>, "vaesef.vs">;
+ def VAESDM_VV : VALUVs2NoVm<0b111011, 0b00000, RISCVVFormat<0b100>, "vaesdm.vv">;
+ def VAESDM_VS : VALUVs2NoVm<0b011010, 0b00000, RISCVVFormat<0b110>, "vaesdm.vs">;
+ def VAESEM_VV : VALUVs2NoVm<0b111101, 0b00000, RISCVVFormat<0b100>, "vaesem.vv">;
+ def VAESEM_VS : VALUVs2NoVm<0b011110, 0b00000, RISCVVFormat<0b110>, "vaesem.vs">;
+ def VAESKF1_VI : VALUVI_CUSTOM1<0b111110, "vaeskf1.vi", rnum_1_10>;
+ def VAESKF2_VI : VALUVI_CUSTOM2<0b111110, "vaeskf2.vi", rnum_1_14>;
+ def VAESKR1_VI : VALUVI_CUSTOM1<0b111111, "vaeskr1.vi", rnum_1_10>;
+ def VAESKR2_VI : VALUVINoVm_CUSTOM1<0b111111, "vaeskr2.vi", rnum_1_10>;
+ def VAESZ_VS : VALUVs2NoVm<0b011111, 0b00000, RISCVVFormat<0b110>, "vaesz.vs">;
+} // Predicates = [HasStdExtZvkns]
+
+let Predicates = [HasStdExtZvkb] in {
+ defm VANDN_V : VALU_IV_V_X_I<"vandn", 0b110011, uimm5>;
+ def VBREV8_V : VALUVs2<0b110100, 0b00000, RISCVVFormat<0b011>, "vbrev8.v">;
+ defm VCLMUL_V : VALUNoVm_IV_V_X<"vclmul", 0b110101>;
+ defm VCLMULH_V : VALUNoVm_IV_V_X<"vclmulh", 0b110110>;
+ def VREV8_V : VALUVs2<0b110100, 0b00000, RISCVVFormat<0b100>, "vrev8.v">;
+ defm VROL_V : VALU_IV_V_X_I<"vrol", 0b110111, uimm5>;
+ defm VROR_V : VALU_IV_V_X_I<"vror", 0b111000, uimm5>;
+} // Predicates = [HasStdExtZvkb]
+
+let Predicates = [HasStdExtZvkg] in {
+ def VGHMAC_VV : VALUVVNoVm<0b110100, RISCVVFormat<0b000>, "vghmac.vv">;
+} // Predicates = [HasStdExtZvkg]
+
+let Predicates = [HasStdExtZvksed] in {
+ def VSM4K_VI : VALUVINoVm<0b111010, "vsm4k.vi", rnum_0_7>;
+ def VSM4R_VV : VALUVs2NoVm<0b111011, 0b00000, RISCVVFormat<0b011>, "vsm4r.vv">;
+} // Predicates = [HasStdExtZvksed]
+
+let Predicates = [HasStdExtZvksh] in {
+ def VSM3C_VI : VALUVINoVm<0b110101, "vsm3c.vi", uimm5>;
+ def VSM3ME_VV : VALUVVNoVm<0b110110, RISCVVFormat<0b011>, "vsm3me.vv">;
+} // Predicates = [HasStdExtZvksh]
+
+let Predicates = [HasStdExtZvknhaOrZvknhb] in {
+ def VSHA2CH_VV : VALUVVNoVm<0b111110, RISCVVFormat<0b011>, "vsha2ch.vv">;
+ def VSHA2CL_VV : VALUVVNoVm<0b111100, RISCVVFormat<0b011>, "vsha2cl.vv">;
+ def VSHA2MS_VV : VALUVVNoVm<0b111101, RISCVVFormat<0b011>, "vsha2ms.vv">;
+} // Predicates = [HasStdExtZvknhaOrZvknhb]
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -373,6 +373,14 @@
: RVInstV<funct6, vs1, opv, (outs VR:$vd),
(ins VR:$vs2, VMaskOp:$vm),
opcodestr, "$vd, $vs2$vm">;
+
+// op vd, vs2 (use vs1 as instruction encoding)
+class VALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
+ : RVInstV<funct6, vs1, opv, (outs VR:$vd),
+ (ins VR:$vs2), opcodestr,
+ "$vd, $vs2"> {
+ let vm = 1;
+}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
//===----------------------------------------------------------------------===//
@@ -1664,4 +1672,5 @@
}
} // Predicates = [HasVInstructionsI64, IsRV64]
+include "RISCVInstrInfoZvk.td" //SIFIVE
include "RISCVInstrInfoVPseudos.td"
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -452,6 +452,62 @@
// tuning CPU names.
def Feature32Bit
: SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;
+
+def FeatureStdExtZvkns
+ : SubtargetFeature<"zvkns", "HasStdExtZvkns", "true",
+ "'Zvkns' (Vector AES Encryption & Decryption (Single Round))", [FeatureStdExtV]>;
+def HasStdExtZvkns : Predicate<"Subtarget->hasStdExtZvkns()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvkns),
+ "'Zvkns' (Vector AES Encryption & Decryption (Single Round))">;
+
+def FeatureStdExtZvknha
+ : SubtargetFeature<"zvknha", "HasStdExtZvknha", "true",
+ "'Zvknha' (Vector SHA-2. (SHA-256 only))", [FeatureStdExtV]>;
+
+def FeatureStdExtZvknhb
+ : SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true",
+ "'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))",
+ [FeatureStdExtZvknha]>;
+def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">,
+ AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb),
+ "'Zvknha' (Vector SHA-2. (SHA-256 only)) "
+ "'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))">;
+
+def FeatureStdExtZvknf
+ : SubtargetFeature<"zvknf", "HasStdExtZvknf", "true",
+ "'Zvknf' (Vector AES Encryption & Decryption (Full Rounds).)", [FeatureStdExtV]>;
+def HasStdExtZvknf : Predicate<"Subtarget->hasStdExtZvknf()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvknf),
+ "'Zvknf' (Vector AES Encryption & Decryption (Full Rounds).)">;
+
+def FeatureStdExtZvkb
+ : SubtargetFeature<"zvkb", "HasStdExtZvkb", "true",
+ "'Zvkb' (Vector Bitmanip instructions for Cryptography.)", [FeatureStdExtV]>;
+def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvkb),
+ "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">;
+
+def FeatureStdExtZvkg
+ : SubtargetFeature<"zvkg", "HasStdExtZvkg", "true",
+ "'Zvkg' (Vector GCM instructions for Cryptography.)", [FeatureStdExtV]>;
+def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvkg),
+ "'Zvkg' (Vector GCM instructions for Cryptography.)">;
+
+def FeatureStdExtZvksed
+ : SubtargetFeature<"zvksed", "HasStdExtZvksed", "true",
+ "'Zvksed' (SM4 Block Cipher Instructions.)", [FeatureStdExtV]>;
+def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvksed),
+ "'Zvksed' (SM4 Block Cipher Instructions.)">;
+
+def FeatureStdExtZvksh
+ : SubtargetFeature<"zvksh", "HasStdExtZvksh", "true",
+ "'Zvksh' (SM3 Hash Function Instructions.)", [FeatureStdExtV]>;
+def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvksh),
+ "'Zvksh' (SM3 Hash Function Instructions.)">;
+
def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -106,6 +106,16 @@
{"svnapot", RISCVExtensionVersion{1, 0}},
{"svinval", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
+
+ // vector crypto
+ {"zvkns", RISCVExtensionVersion{0, 1}},
+ {"zvknha", RISCVExtensionVersion{0, 1}},
+ {"zvknhb", RISCVExtensionVersion{0, 1}},
+ {"zvknf", RISCVExtensionVersion{0, 1}},
+ {"zvkb", RISCVExtensionVersion{0, 1}},
+ {"zvkg", RISCVExtensionVersion{0, 1}},
+ {"zvksed", RISCVExtensionVersion{0, 1}},
+ {"zvksh", RISCVExtensionVersion{0, 1}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
@@ -814,6 +824,14 @@
{{"zve64f"}, {ImpliedExtsZve64f}},
{{"zve64x"}, {ImpliedExtsZve64x}},
{{"zvfh"}, {ImpliedExtsZvfh}},
+ {{"zvkb"}, {ImpliedExtsV}},
+ {{"zvkg"}, {ImpliedExtsV}},
+ {{"zvknf"}, {ImpliedExtsV}},
+ {{"zvknha"}, {ImpliedExtsV}},
+ {{"zvknhb"}, {ImpliedExtsV}},
+ {{"zvkns"}, {ImpliedExtsV}},
+ {{"zvksed"}, {ImpliedExtsV}},
+ {{"zvksh"}, {ImpliedExtsV}},
{{"zvl1024b"}, {ImpliedExtsZvl1024b}},
{{"zvl128b"}, {ImpliedExtsZvl128b}},
{{"zvl16384b"}, {ImpliedExtsZvl16384b}},
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -44,6 +44,14 @@
// CHECK-NOT: __riscv_xventanacondops
// CHECK-NOT: __riscv_zcd
// CHECK-NOT: __riscv_zcf
+// CHECK-NOT: __riscv_zvkns
+// CHECK-NOT: __riscv_zvknha
+// CHECK-NOT: __riscv_zvknhb
+// CHECK-NOT: __riscv_zvknf
+// CHECK-NOT: __riscv_zvkb
+// CHECK-NOT: __riscv_zvkg
+// CHECK-NOT: __riscv_zvksed
+// CHECK-NOT: __riscv_zvksh
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -449,3 +457,51 @@
// RUN: %clang -target riscv32 -march=rv32izcf0p70 -menable-experimental-extensions \
// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
// CHECK-ZCF-EXT: __riscv_zcf 70000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izvkns -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNS-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izvkns -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNS-EXT %s
+// CHECK-ZVKNS-EXT: __riscv_zvkns 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izvknha -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izvknha -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
+// CHECK-ZVKNHA-EXT: __riscv_zvknha 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izvknhb -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izvknhb -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
+// CHECK-ZVKNHB-EXT: __riscv_zvknhb 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izvknf -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNF-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izvknf -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNF-EXT %s
+// CHECK-ZVKNF-EXT: __riscv_zvknf 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izvkb -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izvkb -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s
+// CHECK-ZVKB-EXT: __riscv_zvkb 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izvkg -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izvkg -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
+// CHECK-ZVKG-EXT: __riscv_zvkg 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izvksed -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izvksed -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
+// CHECK-ZVKSED-EXT: __riscv_zvksed 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izvksh -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izvksh -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
+// CHECK-ZVKSH-EXT: __riscv_zvksh 1000{{$}}
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