[PATCH] D121758: [clang-format] Add support for formatting Verilog code

MyDeveloperDay added a comment. In D121758#3389181 , @sstwcw wrote: > Yes. I am surprised that you asked since everyone asked me to break it apart. Well I was thinking you move the unrelated parts out and then reduce the side of this patch, (but you'll

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

sstwcw added a comment. Yes. I am surprised that you asked since everyone asked me to break it apart. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121758/new/ https://reviews.llvm.org/D121758 ___ cfe-c

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

MyDeveloperDay added a comment. Abandoned? huh? are you breaking it apart? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121758/new/ https://reviews.llvm.org/D121758 ___ cfe-commits mailing list cfe-comm

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

HazardyKnusperkeks added a comment. This is an enormous patch. @MyDeveloperDay mentioned different places which could be separate patches, but in addition could the adding of the verilog language be split up, so that one can comprehend the patch in a reasonable time? Comment

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

MyDeveloperDay added a comment. You need to rebase the patch, it doesn't apply. Comment at: clang/lib/Format/Format.cpp:3451 +for (auto Suffix : Lang.second) + if (FileName.endswith(Suffix)) +return Lang.first; krasimir wrote: > I kinda prefer

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

krasimir added inline comments. Comment at: clang/lib/Format/Format.cpp:3451 +for (auto Suffix : Lang.second) + if (FileName.endswith(Suffix)) +return Lang.first; I kinda prefer the old style of handling this I find it simpler to read. I'd be OK

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

MyDeveloperDay added a comment. I'm very much a "clang-format all the things" kind of person which is why I added C# and JSON support, as someone who moves between languages all day every day I want one tool to rule them all.. I'd love it if it would format YAML (but thats another story).. For

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

MyDeveloperDay added inline comments. Comment at: clang/lib/Format/ContinuationIndenter.cpp:1373 + else if (!Current.isOneOf(tok::comment, tok::identifier) && + !Keywords.isPPHash(Current, Style) && !Current.isStringLiteral()) State.StartOfStringLiteral = 0; -

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

MyDeveloperDay added inline comments. Comment at: clang/docs/ClangFormatStyleOptions.rst:2241 +**BreakBetweenInstancePorts** (``Boolean``) :versionbadge:`clang-format 15` + For Verilog, put each port on its own line in module instantiations. I don't feel "Inst

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

MyDeveloperDay added a comment. Firstly thank you for taking the time to submit the patch, I've only taken a cursory view at first and I definitely have some comments, I've added the main clang-format reviewers This is a very invasive patch so there are a number of things we might want to do t

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

sstwcw added a comment. Somehow the bot can't create a branch when trying to merge this patch. The error is failure to lock. The error persists after restarting the process. Does anyone know why? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D12

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

sstwcw added inline comments. Comment at: clang/lib/Format/UnwrappedLineParser.cpp:534 continue; - parseBlock(/*MustBeDeclaration=*/false, /*AddLevels=*/1u, - /*MunchSemi=*/true, /*UnindentWhitesmithBraces=*/false, - CanContainBracedL

[PATCH] D121758: [clang-format] Add support for formatting Verilog code

sstwcw added a subscriber: svenvh. sstwcw added a comment. Do we have people who use Verilog and knows the clang-format code base? @svenvh Your email address looks like you work for a hardware company. If you know Verilog would you please have a look at this patch? Repository: rG LLVM Gith