[PATCH] D109260: [RISCV] Add SiFive cores E and S series

This revision was automatically updated to reflect the committed changes. Closed by commit rG4bc8dbe0cae3: [RISCV] Add SiFive cores E and S series (authored by apivovarov). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.ll

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 ___

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov added a comment. Craig, I fixed all of the issue on Fri. Could you look at the patch again? Thank you Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 __

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov updated this revision to Diff 370692. apivovarov added a comment. fix double space issue. Fri... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 Files: clang/docs/ReleaseNotes.rst clang/tes

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov updated this revision to Diff 370691. apivovarov marked an inline comment as done. apivovarov added a comment. main branch is unstable. pulling the hot fixes again CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 Files: clang/d

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: clang/test/Misc/target-invalid-cpu-note.c:195 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76 +// RISCV32: note: va

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov marked 4 inline comments as done. apivovarov added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:279 + +def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit, + FeatureStdExtM, craig

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov updated this revision to Diff 370687. apivovarov added a comment. fix typos Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 Files: clang/docs/ReleaseNotes.rst clang/test/Driver/riscv-cpus.c

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:24 +PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_E34, {"sifive-e24"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) -

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:24 +PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_E34, {"sifive-e24"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) -

[PATCH] D109260: [RISCV] Add SiFive cores E and S series

apivovarov updated this revision to Diff 370683. apivovarov retitled this revision from "[RISCV] Add SiFive core E20" to "[RISCV] Add SiFive cores E and S series". apivovarov edited the summary of this revision. apivovarov added a comment. Added SiFive cores E20, E21, E24, E34, S21, S54 and S76