apivovarov marked 4 inline comments as done. apivovarov added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCV.td:279 + +def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit, + FeatureStdExtM, ---------------- craig.topper wrote: > Can we sort these by leading digit, then by letter? That will keep most of > the SiFive7Models together. Well, it is sorted by `core_type + number` in all other places in LLVM codebase (including error messages). GCC also sorts them as [[ https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv-cores.def | E-S-U ]]. As well as [[ https://www.sifive.com/risc-v-core-ip | sifive.com ]] Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D109260 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
