[clang] [CIR] floating-point, pointer, and function types (PR #120484)

2024-12-19 Thread Ronan Keryell via cfe-commits
keryell wrote: > My bad here, we usually don't accept such changes and I missed that during > review time. ClangIR policy to changes outside CIR is to upstream them to > MLIR and after that's done we cherry-pick it to the incubator (so rebases are > smooth). I'll have to revert your change, so

[clang] [CIR] floating-point, pointer, and function types (PR #120484)

2024-12-19 Thread Ronan Keryell via cfe-commits
keryell wrote: @dkolsen-pgi Great PR! Since it touches functions returning `!void` or `!cir.void`, I made some changes recently with https://github.com/llvm/clangir/commit/568b51537e573c7a8fb616cda5cdd0aa54bc0832 to avoid disrupting some MLIR invariants. Are you up-streaming the changes in c

[clang] [SYCL] change sycl version accrodnig to standard (PR #114790)

2024-11-22 Thread Ronan Keryell via cfe-commits
keryell wrote: That sounds good. Could you fix the typos in the PR title and the commit messages. Please write SYCL in uppercase everywhere since it is a standard name. https://github.com/llvm/llvm-project/pull/114790 ___ cfe-commits mailing list cfe-c

[clang] [SYCL] The sycl_kernel_entry_point attribute. (PR #111389)

2024-10-30 Thread Ronan Keryell via cfe-commits
@@ -455,6 +455,174 @@ The SYCL kernel in the previous code sample meets these expectations. }]; } +def SYCLKernelEntryPointDocs : Documentation { + let Category = DocCatFunction; + let Content = [{ +The ``sycl_kernel_entry_point`` attribute facilitates the generation of a

[clang] [SYCL] The sycl_kernel_entry_point attribute. (PR #111389)

2024-10-28 Thread Ronan Keryell via cfe-commits
@@ -407,7 +407,8 @@ def MicrosoftExt : LangOpt<"MicrosoftExt">; def Borland : LangOpt<"Borland">; def CUDA : LangOpt<"CUDA">; def HIP : LangOpt<"HIP">; -def SYCL : LangOpt<"SYCLIsDevice">; +def SYCLHost : LangOpt<"SYCLIsHost">; keryell wrote: On the other hand

[clang] [CIR] Call code gen; create empty cir.func op (PR #113483)

2024-10-28 Thread Ronan Keryell via cfe-commits
https://github.com/keryell edited https://github.com/llvm/llvm-project/pull/113483 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CIR] Call code gen; create empty cir.func op (PR #113483)

2024-10-28 Thread Ronan Keryell via cfe-commits
https://github.com/keryell commented: Nice! https://github.com/llvm/llvm-project/pull/113483 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CIR] Call code gen; create empty cir.func op (PR #113483)

2024-10-28 Thread Ronan Keryell via cfe-commits
@@ -0,0 +1,38 @@ +//===- CIRAttrs.cpp - MLIR CIR Attributes -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [SYCL] The sycl_kernel_entry_point attribute. (PR #111389)

2024-10-21 Thread Ronan Keryell via cfe-commits
https://github.com/keryell approved this pull request. LGTM. Thanks for the good documentation! https://github.com/llvm/llvm-project/pull/111389 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[clang] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-12 Thread Ronan Keryell via cfe-commits
@@ -811,8 +812,13 @@ LogicalResult ConvertAllocOpToGpuRuntimeCallPattern::matchAndRewrite( // descriptor. Type elementPtrType = this->getElementPtrType(memRefType); auto stream = adaptor.getAsyncDependencies().front(); + + auto isHostShared = rewriter.create( + loc

[clang-tools-extra] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-12 Thread Ronan Keryell via cfe-commits
@@ -811,8 +812,13 @@ LogicalResult ConvertAllocOpToGpuRuntimeCallPattern::matchAndRewrite( // descriptor. Type elementPtrType = this->getElementPtrType(memRefType); auto stream = adaptor.getAsyncDependencies().front(); + + auto isHostShared = rewriter.create( + loc

[clang-tools-extra] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-07 Thread Ronan Keryell via cfe-commits
@@ -811,8 +812,13 @@ LogicalResult ConvertAllocOpToGpuRuntimeCallPattern::matchAndRewrite( // descriptor. Type elementPtrType = this->getElementPtrType(memRefType); auto stream = adaptor.getAsyncDependencies().front(); + + auto isHostShared = rewriter.create( + loc

[clang] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-07 Thread Ronan Keryell via cfe-commits
@@ -811,8 +812,13 @@ LogicalResult ConvertAllocOpToGpuRuntimeCallPattern::matchAndRewrite( // descriptor. Type elementPtrType = this->getElementPtrType(memRefType); auto stream = adaptor.getAsyncDependencies().front(); + + auto isHostShared = rewriter.create( + loc

[clang] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-07 Thread Ronan Keryell via cfe-commits
https://github.com/keryell edited https://github.com/llvm/llvm-project/pull/65539 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
@@ -116,6 +116,7 @@ add_definitions(-DMLIR_ROCM_CONVERSIONS_ENABLED=${MLIR_ENABLE_ROCM_CONVERSIONS}) set(MLIR_ENABLE_CUDA_RUNNER 0 CACHE BOOL "Enable building the mlir CUDA runner") set(MLIR_ENABLE_ROCM_RUNNER 0 CACHE BOOL "Enable building the mlir ROCm runner") +set(MLIR_E

[clang-tools-extra] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
@@ -0,0 +1,223 @@ +//===- SyclRuntimeWrappers.cpp - MLIR SYCL wrapper library ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-

[clang] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
@@ -0,0 +1,223 @@ +//===- SyclRuntimeWrappers.cpp - MLIR SYCL wrapper library ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-

[clang] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
https://github.com/keryell edited https://github.com/llvm/llvm-project/pull/65539 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
@@ -0,0 +1,223 @@ +//===- SyclRuntimeWrappers.cpp - MLIR SYCL wrapper library ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-

[clang-tools-extra] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
@@ -0,0 +1,223 @@ +//===- SyclRuntimeWrappers.cpp - MLIR SYCL wrapper library ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-

[clang] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
@@ -0,0 +1,223 @@ +//===- SyclRuntimeWrappers.cpp - MLIR SYCL wrapper library ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-

[clang-tools-extra] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
@@ -0,0 +1,223 @@ +//===- SyclRuntimeWrappers.cpp - MLIR SYCL wrapper library ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-

[clang] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
@@ -116,6 +116,7 @@ add_definitions(-DMLIR_ROCM_CONVERSIONS_ENABLED=${MLIR_ENABLE_ROCM_CONVERSIONS}) set(MLIR_ENABLE_CUDA_RUNNER 0 CACHE BOOL "Enable building the mlir CUDA runner") set(MLIR_ENABLE_ROCM_RUNNER 0 CACHE BOOL "Enable building the mlir ROCm runner") +set(MLIR_E

[clang-tools-extra] [MLIR] Enabling Intel GPU Integration. (PR #65539)

2023-09-06 Thread Ronan Keryell via cfe-commits
https://github.com/keryell commented: Quite interesting! At some point it would be nice to have some design document or documentation somewhere explaining how all these MLIR runners works, including this one. Globally this PR add a SYCL runner, but it is very specific for Intel Level 0. It would

[PATCH] D26735: [OpenCL] Disable && (address of label) GNU extension for OpenCL

2016-11-19 Thread Ronan Keryell via cfe-commits
keryell added a comment. +1 Please do not remove anything, since it may be useful in some contexts. I do not think there are negative tests in the Khronos OpenCL conformance test suite anyway. https://reviews.llvm.org/D26735 ___ cfe-commits mailin

Re: [PATCH] D15914: [OpenCL] Pipe builtin functions

2016-01-12 Thread Ronan Keryell via cfe-commits
keryell added a subscriber: keryell. Comment at: include/clang/Basic/Builtins.h:39 @@ -38,2 +38,3 @@ MS_LANG = 0x10, // builtin requires MS mode. + OCLC_LANG = 0x20,// builtin for OpenCL C only. ALL_LANGUAGES = C_LANG | CXX_LANG | OBJC_LANG, // builtin for all languages. -